SLUSD12A October   2017  – February 2018 UCC28780


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      45-W, 20-V GaN-ACF Adapter Efficiency
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. Brown-In and Brown-Out
        2. Output Over-Voltage Protection
        3. Over-Temperature Protection
        4. Programmable Over-Power Protection
        5. Peak Current Limit
        6. Output Short-Circuit Protection
        7. Over-Current Protection
        8. Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. Protections on CS pin Fault
        2. Protections on HVG pin Fault
        3. Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Input Bulk Capacitance and Minimum Bulk Voltage
        2. Transformer Calculations
          1. Primary-to-Secondary Turns Ratio (NPS)
          2. Primary Magnetizing Inductance (LM)
          3. Primary Turns (NP)
          4. Secondary Turns (NS)
          5. Turns of Auxiliary Winding (NA)
          6. Winding and Magnetic Core Materials
        3. Clamp Capacitor Calculation
        4. Bleed-Resistor Calculation
        5. Output Filter Calculation
        6. Calculation of ZVS Sensing Network
        7. Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Over-Voltage Protection

VS pin senses the positive voltage level of the auxiliary winding voltage (VAUX) to detect an over-voltage condition of VO. When an OVP event is triggered, UCC28780 stops switching and there is a 1.5-s fault recovery time (tFDR) before any VO restart attempt is made. As QL turns off, the settled VAUX is equal to (VO+VF) x NAS, where NAS is the auxiliary-to-secondary turns ratio of the transformer, NA / NS, and VF is the forward voltage drop of the secondary-side rectifier. The VS pin senses VAUX through a voltage divider formed by RVS1 and RVS2. The pin voltage (VVS) is compared with an internal OVP threshold (VOVP). If VVS ≥ VOVP condition is qualified for three consecutive PWML pulses, the controller stops switching, brings RUN pin low, and initiates the 1.5-s time delay. During this long delay time, only the UVLO-cycle of VVDD is active, and there are no test pulses of PWML. After the 1.5-s timeout is completed and VVDD reaches the next VVDD(OFF), a normal start sequence begins. The calculation of RVS2 is

Equation 15. UCC28780 Equ-RVS2.gif

The long tFDR timer helps to protect the power stage components from the large current stress during every restart. After OVP is triggered, VO may be brought down quickly by the output load current. If OVP were reset directly after one UVLO cycle of VDD without the 1.5-s delay, the first PWMH pulse turns on QH under the condition of a large voltage difference between the high clamp capacitor voltage (VCLAMP) and the low reflected voltage. A large current can flow through the clamp switch (QH) and secondary rectifier. Therefore, the 1.5-s timer of UCC28780 allows VCLAMP to drop to a lower voltage level through a bleeding resistor (RBLEED) in parallel with CCLAMP before the next VO restart attempt, such that the current stress can be minimized. A large RBLEED can be used with the long time-out to minimize the impact on standby power. For example, to discharge VCLAMP to 10% of its normal level in 1.5 s, only 3 mW of additional standby power is added with RBLEED = 2.8 MΩ and CCLAMP = 220 nF. Figure 32 illustrates the timing sequence as VCLAMP is discharged to a residual voltage (VRESIDUAL) in 1.5 s. RBLEED also helps to reduce the voltage overcharge on the clamp capacitor in LPM and SBP modes in which PWMH is disabled, so the voltage stress in the passive-clamp operation can be controlled.

During LPM to ABM mode transition, it is possible to falsely trigger OVP if the setting does not have enough design margin. In LPM mode with a disabled PWMH, the leakage energy of the transformer charges VCLAMP higher than the reflected voltage. When the controller enters into ABM and the PWMH is enabled, the active-clamp circuit of ACF needs to take some time to balance the voltage difference, depending on the clamp capacitor value. As a result, VAUX can sense the higher VCLAMP condition during the voltage balancing and the controller may treat this as an OVP event, even though VO still stays in regulation and does not reach the actual OVP point. It may only happen with a large CCLAMP design, so slightly increasing the OVP setting can resolve the problem.

UCC28780 Timing-Cclamp.gifFigure 32. Timing Diagram of CCLAMP Discharging During 1.5-s Recovery Time