SLUSD12A October   2017  – February 2018 UCC28780


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      45-W, 20-V GaN-ACF Adapter Efficiency
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. Brown-In and Brown-Out
        2. Output Over-Voltage Protection
        3. Over-Temperature Protection
        4. Programmable Over-Power Protection
        5. Peak Current Limit
        6. Output Short-Circuit Protection
        7. Over-Current Protection
        8. Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. Protections on CS pin Fault
        2. Protections on HVG pin Fault
        3. Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Input Bulk Capacitance and Minimum Bulk Voltage
        2. Transformer Calculations
          1. Primary-to-Secondary Turns Ratio (NPS)
          2. Primary Magnetizing Inductance (LM)
          3. Primary Turns (NP)
          4. Secondary Turns (NS)
          5. Turns of Auxiliary Winding (NA)
          6. Winding and Magnetic Core Materials
        3. Clamp Capacitor Calculation
        4. Bleed-Resistor Calculation
        5. Output Filter Calculation
        6. Calculation of ZVS Sensing Network
        7. Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Protections on CS pin Fault

UCC28780 identifies a fail-short event on the CS pin by monitoring the on-time pulse width of the first PWML pulse after VVDD startup is completed. As shown in Figure 30, the normal first on-time pulse width should be limited by the clamped VCST(SM1) level of 0.28 V and the rising slope of the current-loop feedback signal from the current-sense resistor (RCS) to the CS pin. When the current feedback path is gone due to a CS pin short to GND, the peak magnetizing current increases and potentially can damage the power stage. Therefore, a maximum on-time of the first PWML pulse under VSET = 5 V, tCSF1 of 2 μs in the electrical table, is used to limit the first peak-current stress of the silicon-based converter and then will trigger a CS pin short protection which initiates the tFDR recovery of 1.5 s.

Additionally, tCSF0 in the electrical table confines the maximum on-time of the first PWML pulse on the GaN-based converter with VSET = 0 V. There are two corresponding values based on two predetermined ranges of the RDM pin setting in order to provide the protection over a wider switching frequency range. Specifically, tCSF0 is set at 2 μs with RRDM higher than the RRDM(TH) threshold of 50 kΩ, while tCSF0 is reduced to 1 μs under RRDM < RRDM(TH). Since a GaN-based converter is capable of operating at higher switching frequency by lowering the magnetizing inductance (LM), it is possible that the peak current can increase higher than a lower switching-frequency design under the same VCST(SM1) level and same on-time of PWML. The RDM pin can provide a good indication on the switching frequency range of a GaN power stage, since the lower LM requires smaller RRDM setting. With a different tCSF0 setting, the CS pin fault adapts to a wide switching frequency range.

Unlike a CS pin short protection which senses the first on-time pulse width of PWML only, CS pin open protection monitors the fail-open condition cycle-by-cycle. An internal 4-μA current source out of the CS pin is used to pull the CS pin voltage up to 3.3 V as the CS pin exhibits high impedance during a fail-open condition. When the CS voltage is higher than the 1.2-V threshold of the OCP limit and lasts for three consecutive PWML pulses, the CS pin open protection is triggered which initiates the 1.5-s recovery.