SLUSD12A October   2017  – February 2018 UCC28780


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      45-W, 20-V GaN-ACF Adapter Efficiency
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. Brown-In and Brown-Out
        2. Output Over-Voltage Protection
        3. Over-Temperature Protection
        4. Programmable Over-Power Protection
        5. Peak Current Limit
        6. Output Short-Circuit Protection
        7. Over-Current Protection
        8. Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. Protections on CS pin Fault
        2. Protections on HVG pin Fault
        3. Protections on RDM and RTZ pin Faults
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Input Bulk Capacitance and Minimum Bulk Voltage
        2. Transformer Calculations
          1. Primary-to-Secondary Turns Ratio (NPS)
          2. Primary Magnetizing Inductance (LM)
          3. Primary Turns (NP)
          4. Secondary Turns (NS)
          5. Turns of Auxiliary Winding (NA)
          6. Winding and Magnetic Core Materials
        3. Clamp Capacitor Calculation
        4. Bleed-Resistor Calculation
        5. Output Filter Calculation
        6. Calculation of ZVS Sensing Network
        7. Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

VDD Pin (Device Bias Supply)

The VDD pin is the primary bias for the internal 5-V REF regulator, internal 11-V HVG regulator, other internal references, and the undervoltage lock-out (UVLO) circuit. As shown in Functional Block Diagram, the UVLO circuit connected to the VDD pin controls three power-path switches among VDD, HVG, and SWS pins, in order to allow QS to be able to perform both VVDD startup and VSW sensing for ZVS control after startup. During startup, SWS and HVG pins are connected to VDD pin allowing an external depletion-mode MOSFET (QS) to charge the VDD capacitor (CVDD) from the switch-node voltage (VSW). After VDD startup competes, the ZVS discriminator block is enabled, so as switching logics. Then, the transformer starts delivering energy to the output capacitor (CO) every switching cycle, so both output voltage (VO) and auxiliary winding voltage (VAUX) increase. As VAUX is high enough, the auxiliary winding will take over to power VVDD. The UVLO circuit provides a turn-on threshold of VVDD(ON) at 17.5 V and turn-off threshold of VVDD(OFF) at 9.8 V. The range can accommodate lower values of VDD capacitor (CVDD) and support shorter power-on delays. 38-V maximum operating level on VVDD alleviates concerns with leakage energy charging of CVDD and gives added flexibility when a varying output voltage must be supported.

As VVDD reaches VVDD(ON) , SWS pin is disconnected from the VDD pin, so the CVDD size has to be sufficient to hold VVDD higher than VVDD(OFF) until the positive auxiliary winding voltage is high enough to take over bias power delivery during VO soft start. Therefore, the calculation of minimum capacitance (CVDD(MIN)) needs to consider the discharging effect from the sink current of the UCC28780 during switching in its run state (IRUN(SW)), the average operating current of driver (IDR), and the average gate charge current of half-bridge FETs (IQg) throughout the longest time of VO soft start (tSS(MAX)).

Equation 4. UCC28780 Equ-CDDmin.gif

tSS(MAX) estimation should consider the averaged soft-start current (ISEC(SS)) on the secondary side of ACF, the constant-current output load (IO(SS)) (if any), maximum output capacitance (CO(MAX)), and a 1-ms time-out potentially being triggered in the startup sequence.

Equation 5. UCC28780 Equ-tssmax.gif

During VO soft start, VCST reaches the maximum current threshold on the CS pin (VCST(MAX)) , so ISEC(SS) at the minimum voltage of the input bulk capacitor (VBULK(MIN)) can be approximated as:

Equation 6. UCC28780 Equ-isecss.gif

where RCS is the current sense resistor, NPS is primary-to-secondary turns ratio, and VF is the forward voltage drop of the secondary rectifier.

For details of the startup sequencing, one can refer to the Device Functional Modes of this datasheet.