Table 1. UCC28950 Typical Application Design Requirements

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
	INPUT CHARACTERISTICS
VIN	DC input voltage range		370	390	410	V
IIN(max)	Maximum input current	VIN= 370 VDC to 410 VDC			2	A
	OUTPUT CHARACTERISTICS
VOUT	Output voltage	VIN= 370 VDC to 410 VDC	11.4	12	12.6	V
IOUT	Output current	VIN= 370 VDC to 410 VDC			50	A
	Output voltage transient	90% load step		600		mV
POUT	Continuous output power	VIN= 370 VDC to 410 VDC			600	W
	Load regulation	VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A			140	mV
	Line regulation	VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A			140	mV
	Output ripple voltage	VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A			200	mV
	SYSTEM
FSW	Switching Frequency			100		kHz
	Full-load efficiency	VIN= 370 VDC to 410 VDC, POUT= 500 W	93%	94%

8.2.2.1 Power Loss Budget

To meet the efficiency goal a power loss budget needs to be set.

8.2.2.2 Preliminary Transformer Calculations (T1)

Transformer turns ratio (a1):

Estimated FET voltage drop (V_RDSON):

Select transformer turns based on 70% duty cycle (D_MAX) at minimum specified input voltage. This will give some room for dropout if a PFC front end is used.

Turns ratio rounded to the nearest whole turn.

Calculated typical duty cycle (D_TYP) based on average input voltage.

Output inductor peak-to-peak ripple current is set to 20% of the output current.

Care must be taken in selecting the correct amount of magnetizing inductance (L_MAG). The following equations calculate the minimum magnetizing inductance of the primary of the transformer (T1) to ensure the converter operates in current-mode control. As L_MAG reduces, the increasing magnetizing current becomes an increasing proportion of the signal at the CS pin. If the magnetizing current increases enough it can swamp out the current sense signal across R_CS and the converter will operate increasingly as if it were in voltage mode control rather than current mode.

Figure 49 shows T1 primary current (I_PRIMARY) and synchronous rectifiers QE (I_QE) and QF (I_QF) currents with respect to the synchronous rectifier gate drive currents. Note that I_QE and I_QF are the same as the secondary winding currents of T1. Variable D is the duty cycle of the converter.

Calculate T1 secondary RMS current (I_SRMS):

Secondary RMS current (I_SRMS1) when energy is being delivered to the secondary:

Secondary RMS current (I_SRMS2) when current is circulating through the transformer when QE and QF are both on.

Secondary RMS current (I_SRMS3) caused by the negative current in the opposing winding during freewheeling period, please refer to Figure 49.

Total secondary RMS current (I_SRMS):

Calculate T1 Primary RMS Current (I_PRMS):

T1 Primary RMS (I_PRMS1) current when energy is being delivered to the secondary.

T1 Primary RMS (I_PRMS2) current when the converter is free wheeling.

Total T1 primary RMS current (I_PRMS):

For this design a Vitec™ transformer was selected part number 75PR8107 that had the following specifications.

Measure leakage inductance on the Primary:

Transformer Primary DC resistance:

Transformer Secondary DC resistance:

Estimated transformer core losses (P_T1) are twice the copper loss.

NOTE

This is just an estimate and the total losses may vary based on magnetic design.

Calculate remaining power budget:

8.2.2.3 QA, QB, QC, QD FET Selection

In this design to meet efficiency and voltage requirements 20 A, 650 V, CoolMOS FETs from Infineon are chosen for QA..QD.

FET drain to source on resistance:

FET Specified C_OSS:

Voltage across drain-to-source (V_dsQA) where C_OSS was measured, data sheet parameter:

Calculate average C_oss [2]:

QA FET gate charge:

Voltage applied to FET gate to activate FET:

Calculate QA losses (P_QA) based on R_ds(on)QA and gate charge (QA_g):

Recalculate power budget:

8.2.2.4 Selecting L_S

Calculating the value of the shim inductor (L_S) is based on the amount of energy required to achieve zero voltage switching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switch node. The following equation selects L_S to achieve ZVS at 100% load down to 50% load based on the primary FET’s average total C_OSS at the switch node.

NOTE

The actual parasitic capacitance at the switched node may differ from the estimate and L_S may have to be adjusted accordingly.

For this design a 26-µH Vitec inductor was chosen for L_S, part number 60PR964. The shim inductor had the following specifications.

L_S DC Resistance:

Estimate L_S power loss (P_LS) and readjust remaining power budget:

8.2.2.5 Selecting Diodes D_B and D_C

There is a potential for high voltage ringing on the secondary rectifiers, caused by the difference in current between the transformer and the shim inductor when the transformer comes out of freewheeling. Diodes D_B and D_C provide a path for this current and prevent any ringing by clamping the transformer primary to the primary side power rails. Normally these diodes do not dissipate much power but they should be sized to carry the full primary current. The worse case power dissipated in these diodes is:

The diodes should be ultra-fast types and rated for the input voltage of the converter – V_IN (410 VDC in this case).

A MURS360 part is suitable at this power level.

8.2.2.6 Output Inductor Selection (L_OUT)

Inductor L_OUT is designed for 20% inductor ripple current (∆I_LOUT):

Calculate output inductor RMS current (I_{LOUT_RMS}):

A 2-µH inductor from Vitec Electronics Corporation, part number 75PR8108, is suitable for this design. The inductor has the following specifications.

Output inductor DC resistance:

Estimate output inductor losses (P_LOUT) and recalculate power budget. Note P_LOUT is an estimate of inductor losses that is twice the copper loss. Note this may vary based on magnetic manufactures. It is advisable to double check the magnetic loss with the magnetic manufacture.

8.2.2.7 Output Capacitance (C_OUT)

The output capacitor is selected based on holdup and transient (V_TRAN) load requirements.

Time it takes L_OUT to change 90% of its full load current:

During load transients most of the current will immediately go through the capacitors equivalent series resistance (ESR_COUT). The following equations are used to select ESR_COUT and C_OUT based on a 90% load step in current. The ESR is selected for 90% of the allowable transient voltage (V_TRAN), while the output capacitance (C_OUT) is selected for 10% of V_TRAN.

Before selecting the output capacitor, the output capacitor RMS current (I_{COUT_RMS}) must be calculated.

To meet the design requirements five 1500-µF, aluminum electrolytic capacitors are chosen for the design from United Chemi-Con™, part number EKY-160ELL152MJ30S. These capacitors have an ESR of 31 mΩ.

Number of output capacitors:

Total output capacitance:

Effective output capacitance ESR:

Calculate output capacitor loss (P_COUT):

Recalculate remaining Power Budget:

8.2.2.8 Select FETs QE and QF

Selecting FETs for a design is an iterative process. To meet the power requirements of this design, we select 75-V, 120-A FETs, from Fairchild, part number FDP032N08. These FETs have the following characteristics.

Calculate average FET C_OSS (C_{OSS_QE_AVG}) based on the data sheet parameters for C_OSS (C_{OSS_SPEC}), and drain to source voltage where C_{OSS_SPEC} was measured (V_{ds_spec}), and the maximum drain to source voltage in the design (V_dsQE) that will be applied to the FET in the application.

Voltage across FET QE and QF when they are off:

Voltage where FET C_OSS is specified and tested in the FET data sheet:

Specified output capacitance from FET data sheet:

Average QE and QF C_OSS [2]:

QE and QF RMS current:

To estimate FET switching loss the V_g vs. Q_g curve from the FET data sheet needs to be studied. First the gate charge at the beginning of the miller plateau needs to be determined (QE_{MILLER_MIN}) and the gate charge at the end of the miller plateau (QE_{MILLER_MAX}) for the given V_DS.

Maximum gate charge at the end of the miller plateau:

Minimum gate charge at the beginning of the miller plateau:

NOTE

The FETs in this design are driven with a UCC27324 Gate Driver IC, setup to drive 4-A (I_P) of gate drive current.

Estimated FET V_ds rise and fall time:

Estimate QE and QF FET Losses (P_QE):

Recalculate the power budget.

8.2.2.9 Input Capacitance (C_IN)

The input voltage in this design is 390 V_DC, which is generally fed by the output of a PFC boost pre-regulator. The input capacitance is generally selected based on holdup and ripple requirements.

NOTE

The delay time needed to achieve ZVS can act as a duty cycle clamp (D_CLAMP).

Calculate tank frequency:

Estimated delay time:

Effective duty cycle clamp (D_CLAMP):

V_DROP is the minimum input voltage where the converter can still maintain output regulation. The converter’s input voltage would only drop down this low during a brownout or line-drop condition if this converter was following a PFC pre-regulator.

C_IN was calculated based on one line cycle of holdup:

Calculate high frequency input capacitor RMS current (I_CINRMS).

To meet the input capacitance and RMS current requirements for this design a 330-µF capacitor was chosen from Panasonic part number EETHC2W331EA.

This capacitor has a high frequency (ESR_CIN) of 150 mΩ, measured with an impedance analyzer at 200 kHz.

Estimate C_IN power dissipation (P_CIN):

Recalculate remaining power budget:

There is roughly 6.0 W left in the power budget left for the current sensing network, and biasing the control device and all resistors supporting the control device.

8.2.2.10 Current Sense Network (CT, R_CS, R7, D_A)

The CT chosen for this design has a turns ratio (CT_RAT) of 100:1

Calculate nominal peak current (I_P1) at V_INMIN:

Peak primary current:

The CS pin voltage where peak current limit will trip.

Calculate current sense resistor (R_CS) and leave 300mV for slope compensation. Include a 1.1 factor for margin:

Select a standard resistor for R_CS:

Estimate power loss for R_CS:

Calculate maximum reverse voltage (V_DA) on D_A:

Estimate D_A power loss (P_DA):

Calculate reset resistor R7:

Resistor R7 is used to reset the current sense transformer CT.

Resistor R_LF1 and capacitor C_LF form a low pass filter for the current sense signal (Pin 15). For this design we chose the following values. This filter has a low frequency pole (f_LFP) at 482 kHz. This should work for most applications but may be adjusted to suit individual layouts and EMI present in the design.

The UCC28950 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency noise. This pin needs at least 1 µF of high frequency bypass capacitance (C_REF).

The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (R1, R2), for this design example, the error amplifier reference voltage (V1) will be set to 2.5 V. Select a standard resistor value for R1 and then calculate resistor value R2.

UCC28950 reference voltage:

Set voltage amplifier reference voltage:

Voltage divider formed by resistor R3 and R4 are chosen to set the DC output voltage (V_OUT) at Pin 3 (EA-).

Select a standard resistor for R3:

Calculate R4:

Then choose a standard resistor for R4:

Compensating the feedback loop can be accomplished by properly selecting the feedback components (R5, C1 and C2). These components are placed as close as possible to pin 3 and 4 of the UCC28950. A Type 2 compensation network is designed in this example.

Calculate load impedance at 10% load (R_LOAD):

Approximation of control to output transfer function (G_CO(f)) as a function of frequency:

Double pole frequency of G_CO(f):

Angular velocity:

Compensate the voltage loop with type 2 feedback network. The following transfer function is the compensation gain as a function of frequency (G_C(f)).

Calculate voltage loop feedback resistor (R5) based on crossing the voltage loop (f_C) over at a 10^th of the double pole frequency (f_PP).

Select a standard resistor for R5.

Calculate the feedback capacitor (C2) to give added phase at crossover.

Select a standard capacitance value for the design.

Put a pole at two times f_C.

Select a standard capacitance value for the design.

Loop gain as a function of frequency (T_V(f)) in dB.

Plot theoretical loop gain and phase to graphically check for loop stability (Figure 51). The theoretical loop gain crosses over at roughly 3.7 kHz with a phase margin of greater than 90 degrees.

NOTE

TI recommends checking your loop stability of your final design with transient testing and/or a network analyzer and adjust the compensation (G_C(f)) feedback as necessary.

To limit over shoot during power up the UCC28950 has a soft-start function (SS, Pin 5) which in this application was set for a soft start time of 15 ms (t_SS).

Select a standard capacitor for the design.

This application note presents a fixed delay approach to achieving ZVS from 100% load down to 50% load. Adaptive delays can be generated by connecting the ADEL and ADELEF pins to the CS pin as shown in Figure 52.

When the converter is operating below 50% load the converter will be operating in valley switching. In order to achieve zero voltage switching on switch node of QB_d, the turn-on (t_ABSET) delays of FETs QA and QB need to be initially set based on the interaction of L_S and the theoretical switch node capacitance. The following equations are used to set t_ABSET initially.

Equate shim inductance to two times C_OSS capacitance:

Calculate tank frequency:

Set initial t_ABSET delay time and adjust as necessary.

NOTE

The 2.25 factor of the t_ABSET equation was derived from empirical test data and may vary based on individual design differences.

The resistor divider formed by R_A and R_AHI programs the t_ABSET, t_CDSET delay range of the UCC28950. Select a standard resistor value for R_AHI.

NOTE

t_ABSET can be programmed between 30 ns to 1000 ns.

The voltage at the ADEL input of the UCC28950 (V_ADEL) needs to be set with R_A based on the following conditions.

If t_ABSET > 155 ns set V_ADEL = 0.2 V, t_ABSET can be programmed between 155 ns and 1000 ns:

If t_ABSET ≤ 155 ns set V_ADEL = 1.8 V, t_ABSET can be programmed between 29 ns and 155 ns:

Based on V_ADEL selection, calculate R_A:

Select the closest standard resistor value for R_A:

Recalculate V_ADEL based on resistor divider selection:

Resistor R_AB programs t_ABSET:

Select a standard resistor value for the design:

NOTE

Once you have a prototype up and running it is recommended you fine tune t_ABSET at light load to the peak and valley of the resonance between L_S and the switch node capacitance. In this design the delay was set at 10% load. Please refer to Figure 53.

The QC and QD turnon delays (t_CDSET) should be initially set for the same delay as the QA and QB turn on delays (Pin 6). The following equations program the QC and QD turn-on delays (t_CDSET) by properly selecting resistor R_DELCD (Pin 7).

Resistor R_CD programs t_CDSET:

Select a standard resistor for the design:

NOTE

Once you have a prototype up and running it is recommended to fine tune t_CDSET at light load. In this design the CD node was set to valley switch at roughly 10% load. Please refer to Figure 54. Obtaining ZVS at lighter loads with switch node QD_d is easier due to the reflected output current present in the primary of the transformer at FET QD and QC turnoff/on. This is because there was more peak current available to energize L_S before this transition, compared to the QA and QB turnoff/on.

There is a programmable delay for the turnoff of FET QF after FET QA turnoff (t_AFSET) and the turnoff of FET QE after FET QB turnoff (t_BESET). A good place to set these delays is 50% of t_ABSET. This will ensure that the appropriate synchronous rectifier turns off before the AB ZVS transition. If this delay is too large it will cause OUTE and OUTF not to overlap correctly and it will create excess body diode conduction on FETs QE and QF.

The resistor divider formed by R_AEF and R_AEFHI programs the t_AFSET and t_BESET delay range of the UCC28950. Select a standard resistor value for R_AEFHI.

NOTE

t_EFSET and t_BESET can be programmed between 32 ns to 1100 ns.

The voltage at the ADELEF pin of the UCC28950 (V_ADELEF) needs to be set with R_AEF based on the following conditions.

If t_AFSET < 170 ns set V_ADEL = 0.2 V, t_ABSET can be programmed between 32 ns and 170 ns:

If t_ABSET > or = 170 ns set V_ADEL = 1.7 V, t_ABSET can be programmed between 170 ns and 1100 ns:

Based on V_ADELEF selection, calculate R_AEF:

Select the closest standard resistor value for R_AEF:

Recalculate V_ADELEF based on resistor divider selection:

The following equation was used to program t_AFSET and t_BESET by properly selecting resistor R_EF.

A standard resistor was chosen for the design.

Resistor R_TMIN programs the minimum on time (t_MIN) that the UCC28950 (Pin 9) can demand before entering burst mode. If the UCC28950 controller tries to demand a duty cycle on time of less than t_MIN the power supply will go into burst mode operation. For this design we set the minimum on time to 75 ns.

The minimum on time is set by selecting R_TMIN with the following equation.

A standard resistor value is then chosen for the design.

A resistor from the RT pin to ground sets the converter switching frequency.

Select a standard resistor for the design.

The UCC28950 provides slope compensation. The amount of slope compensation is set by the resistor R_SUM. As suggested earlier, we set the slope compensation ramp to be half the inductor current ramp downslope (inductor current ramp during the off time), reflected through the main transformer and current sensing networks as explained earlier in Slope Compensation (RSUM).

The required slope compensation ramp is

The magnetizing current of the power transformer provides part of the compensating ramp and is calculated from Equation 169.

The required compensating ramp is

The value for the resistor, R_SUM, may be found from the graph in Figure 37 or calculated from rearranged versions of Equation 12 or Equation 13 depending on whether the controller is operating in Current or Voltage Control Mode. In this case we are using Current Mode Control and Equation 12 is rearranged and evaluated as follows

Check that the 300mV we allowed for the slope compensation ramp when choosing R_CS in Equation 110 is sufficient.

To increase efficiency at lighter loads the UCC28950 is programmed (Pin 12, DCM) under light load conditions to disable the synchronous FETs on the secondary side of the converter (Q_E and Q_F). This threshold is programmed with resistor divider formed by R_DCMHI and R_DCM. This DCM threshold needs to be set at a level before the inductor current goes discontinuous. The following equation sets the level at which the synchronous rectifiers are disabled at roughly 15% load current.

Select a standard resistor value for R_DCM.

Calculate resistor value R_DCMHI.

Select a standard resistor value for this design