SLUSA16D March   2010  – November 2016 UCC28950

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Start-Up Protection Logic
      2. 7.3.2  Voltage Reference (VREF)
      3. 7.3.3  Error Amplifier (EA+, EA-, COMP)
      4. 7.3.4  Soft Start and Enable (SS/EN)
      5. 7.3.5  Light-Load Power Saving Features
      6. 7.3.6  Adaptive Delay, (Delay between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 7.3.7  Adaptive Delay (Delay between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF))
      8. 7.3.8  Minimum Pulse (TMIN)
      9. 7.3.9  Burst Mode
      10. 7.3.10 Switching Frequency Setting
      11. 7.3.11 Slope Compensation (RSUM)
      12. 7.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 7.3.13 Current Sensing (CS)
      14. 7.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 7.3.15 Synchronization (SYNC)
      16. 7.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 7.3.17 Supply Voltage (VDD)
      18. 7.3.18 Ground (GND)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select FETs QE and QF
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 8.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from C Revision (November 2015) to D Revision

  • Changed Pin Functions table to be alphabetized. Go
  • Added text to UCC28950 Startup Timing Diagram note, "Narrower pulse widths (less than 50% duty cycle) may be observed in the first OUTD pulse of a burst. The user must design the bootstrap capacitor charging circuit of the gate driver device so that the first OUTC pulse is transmitted to the MOSFET gate in all cases. Transformer based gate driver circuits are not affected. This behavior is described in more detail in the application note, Gate Driver Design Considerations".Go

Changes from B Revision (October 2011) to C Revision

  • Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Moved Standard Temperature Range from ESD table to Absolute Maximum Ratings table Go
  • Changed Figure 6 Startup Current value from mA to µA.Go
  • Changed Figure 11 Nominal Switching Frequency value from Hz to kHz.Go
  • Changed Figure 12 Maximum Switching Frequency value from Hz to kHz. Go
  • Updated Adaptive Delay section.Go
  • Changed values in Equation 3 Go
  • Changed values in Equation 4 Go
  • Changed line in Figure 34 to stop at RTMIN= 10 kΩ and TMIN = 800 ns.Go
  • Changed content in Slope Compensation (RSUM) section.Go
  • Added TMIN setting to Figure 39.Go
  • Updated Synchronization (SYNC) section.Go
  • Changed Detailed Design Procedure in the Typical Application section.Go
  • Deleted Vg vs. Qg for QE and QF FETs graph from Select FETs QE and QF section.Go
  • Added Daughter Board Schematic. Go
  • Added Power Stage Schematic. Go

Changes from A Revision (July 2010) to B Revision

  • Added Naturally Handles Pre-Biased Start Up with DCM Mode bulletGo
  • Added Datacom, Telecom, and Wireless Base-Station PowerGo
  • Changed Server, Telecom Power Supplies bullet to Server, Power SuppliesGo

Changes from * Revision (March 2010) to A Revision

  • Changed UCC28950 Typical Application DiagramGo
  • Changed Converter switching frequency from 1400 kHz to 1000 kHzGo
  • Changed Functional Block DiagramGo
  • Added Figure 30Go
  • Changed EquationGo
  • Added Typical Application DiagramGo
  • Added always deliver even number of Power cycles to Power transformer.Go
  • Deleted deliver either one or two power delivery cycle pulses. If controller delivers a power delivery cycle for OUTB and OUTC, then it stops. If it starts delivering to OUTA and OUTD, then it continues with another power delivery cycle to OUTB and OUTC, and then it stops.Go