SLUSDB2A August   2018  – December 2021 UCC28951

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Start-Up Protection Logic
      2. 7.3.2  Voltage Reference (VREF)
      3. 7.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 7.3.4  Soft-Start and Enable (SS/EN)
      5. 7.3.5  Light-Load Power Saving Features
      6. 7.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 7.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 7.3.8  Minimum Pulse (TMIN)
      9. 7.3.9  Burst Mode
      10. 7.3.10 Switching Frequency Setting
      11. 7.3.11 Slope Compensation (RSUM)
      12. 7.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 7.3.13 Current Sensing (CS)
      14. 7.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 7.3.15 Synchronization (SYNC)
      16. 7.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 7.3.17 Supply Voltage (VDD)
      18. 7.3.18 Ground (GND)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select FETs QE and QF
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 8.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.10 Current Sense Network (CT, RCS, R7, DA)

The CT chosen for this design has a turns ratio (CTRAT) of 100:1 in Equation 97:

Equation 97. GUID-2DC70411-3AA4-451B-BC6A-CC6DC3107F10-low.gif

Calculate nominal peak current (IP1) at VINMIN:

The peak primary current is calculated using Equation 98:

Equation 98. GUID-DA8C146B-C924-4F52-AAEC-0735681A2A9C-low.gif

The CS pin voltage where peak current limit will trip is:

Equation 99. GUID-6EA58EE2-6F2A-4813-9BCA-FBCF91E6428A-low.gif

Calculate current sense resistor (RCS) and leave 300 mV for slope compensation using Equation 100. Include a 1.1 factor for margin:

Equation 100. GUID-2A0830CE-12D6-4859-A191-0AAD91341272-low.gif

Select a standard resistor for RCS:

Equation 101. GUID-1DCF5A36-076E-4708-9234-A17881A55D2B-low.gif

Estimate the power loss for RCS using Equation 102:

Equation 102. GUID-147DA359-26C4-486B-806F-70EB08372827-low.gif

Calculate maximum reverse voltage (VDA) on DA using Equation 103:

Equation 103. GUID-925CE0AE-F6BA-4297-A6C0-A35F14B28698-low.gif

Estimate the DA power loss (PDA) using Equation 104:

Equation 104. GUID-A3681A43-FF64-4046-9027-4A5DA8C95488-low.gif

Calculate reset resistor R7:

Resistor R7 is used to reset the current sense transformer CT:

Equation 105. GUID-5C6AFD56-96AB-41B3-BC9E-58957C82303A-low.gif

Resistor RLF1 and capacitor CLF form a low-pass filter for the current sense signal (Pin 15). For this design, chose the following values. This filter has a low frequency pole (fLFP) at 482 kHz, (which is appropriate for most applications) but may be adjusted to suit individual layouts and EMI present in the design.

Equation 106. GUID-BC4FE271-5A47-497C-8842-C245B6587A43-low.gif
Equation 107. GUID-0AA2EF9C-A590-4D2B-A373-BF336107F004-low.gif
Equation 108. GUID-1A4D20E7-DD80-4290-A4CE-FCAD2F886BC0-low.gif

The UCC28951 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency noise. This pin needs at least 1 µF of high-frequency bypass capacitance (CREF).

Equation 109. GUID-01A3DF4F-10D1-4279-8B70-1D51FE329683-low.gif

The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (R1, R2), for this design example, the error amplifier reference voltage (V1) will be set to 2.5 V. Select a standard resistor value for R1 and then calculate resistor value R2.

UCC28951 reference voltage:

Equation 110. GUID-85CB9CFC-4C13-42CF-93B8-14488A9D6BFA-low.gif

Set voltage amplifier reference voltage:

Equation 111. GUID-4AFD1611-9996-4C40-80D6-64941C303083-low.gif
Equation 112. GUID-9D0D98D5-C304-481D-8C65-930917BC804E-low.gif
Equation 113. GUID-56CC8105-A818-4C03-A483-7309CEF60C1E-low.gif

The voltage divider formed by resistor R3 and R4 are chosen to set the DC output voltage (VOUT) at Pin 3 (EA-).

Select a standard resistor for R3:

Equation 114. GUID-F3E784A4-7669-4FFA-B636-35C268576115-low.gif

Calculate R4 using Equation 115:

Equation 115. GUID-01891053-9237-4FA3-BB36-DFFCB9D2FA91-low.gif

Then choose a standard resistor for R4 using Equation 116:

Equation 116. GUID-DAE822D7-4E37-487F-BD56-95A5B6B95003-low.gif
Note:

TI recommends using an RCD clamp to protect the output synchronous FETs from overvoltage due to switch node ringing.

GUID-F8A0EEAE-3145-47CE-96D6-C6BA40EAFE04-low.gif Figure 8-5 Daughter Board Schematic