SLUSDB2A August   2018  – December 2021 UCC28951


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Start-Up Protection Logic
      2. 7.3.2  Voltage Reference (VREF)
      3. 7.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 7.3.4  Soft-Start and Enable (SS/EN)
      5. 7.3.5  Light-Load Power Saving Features
      6. 7.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 7.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 7.3.8  Minimum Pulse (TMIN)
      9. 7.3.9  Burst Mode
      10. 7.3.10 Switching Frequency Setting
      11. 7.3.11 Slope Compensation (RSUM)
      12. 7.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 7.3.13 Current Sensing (CS)
      14. 7.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 7.3.15 Synchronization (SYNC)
      16. 7.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 7.3.17 Supply Voltage (VDD)
      18. 7.3.18 Ground (GND)
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Power Loss Budget
        2.  Preliminary Transformer Calculations (T1)
        3.  QA, QB, QC, QD FET Selection
        4.  Selecting LS
        5.  Selecting Diodes DB and DC
        6.  Output Inductor Selection (LOUT)
        7.  Output Capacitance (COUT)
        8.  Select FETs QE and QF
        9.  Input Capacitance (CIN)
        10. Current Sense Network (CT, RCS, R7, DA)
          1. Voltage Loop Compensation Recommendation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

To increase the reliability and robustness of the design, TI recommends the following layout guidelines:

  • For the VREF pin: decouple this pin to GND with a good quality ceramic capacitor. A 1-µF, X7R, 25-V capacitor is recommended. Keep VREF PCB tracks as far away as possible from sources of switching noise.
  • For the EA+ pin: this is the noninverting input to the error amplifier. It is a high impedance pin and is susceptible to noise pickup. Keep tracks from this pin as short as possible.
  • For theEA– pin: this is the inverting input to the error amplifier. It is a high impedance pin and is susceptible to noise pickup. Keep tracks from this pin as short as possible.
  • For theCOMP pin: the error amplifier compensation network is normally connected to this pin. Keep tracks from this pin as short as possible.
  • For theSS/EN pin: keep tracks from this pin as short as possible. If the Enable signal is coming from a remote source then avoid running it close to any source of high dv/dt (MOSFET Drain connections for example) and add a simple RC filter at the SS/EN pin.
  • For the DELAB, DELCD, DELEF, TMIN, RT, RSUM, DCM, ADELEF and ADEL pins: the components connected to these pins are used to set important operating parameters. Keep these components close to the IC and provide short, low impedance return connections to the GND pin.
  • For the CS pin: this connection is arguably the most important single connection in the entire PSU system. Avoid running the CS signal traces near to sources of high dv/dt. Provide a simple RC filter as close to the pin as possible to help filter out leading edge noise spikes which occur at the beginning of each switching cycle.
  • For the SYNC pin: this pin is essentially a digital I/O port. If it is unused, then it may be left open circuit or tied to ground through a 1-kΩ resistor. If Synchronisation is used, then route the incoming Synchronisation signal as far away from noise sensitive input pins as possible.
  • For the OUTA, OUTB, OUTC, OUTD, OUTE and OUTF pins: these are the gate drive output pins. They have a high dv/dt rate associated with their rising and falling edges. Keep the tracks from these pins as far away from noise sensitive input pins as possible. Ensure that the return currents from these outputs do not cause voltage changes in the analog ground connections to noise sensitive input pins. Follow the layout recommendation for analog and power ground planes in Figure 7-18.
  • For the VDD pin: this pin must be decoupled to GND using ceramic capacitors as detailed in the Section 9 section. Keep this capacitor as close to the VDD and GND pins as possible.
  • For the GND pin: this pin provides the ground reference to the controller. Use a ground plane to minimize the impedance of the ground connection and to reduce noise pickup.