SLUSDB2A August   2018  – December 2021

PRODUCTION DATA

1. Features
2. Applications
3. Description
4. Revision History
5. Pin Configuration and Functions
6. Specifications
7. Detailed Description
8. Application and Implementation
1. 8.1 Application Information
2. 8.2 Typical Application
1. 8.2.1 Design Requirements
2. 8.2.2 Detailed Design Procedure
3. 8.2.3 Application Curves
9. Power Supply Recommendations
10. 10Layout
11. 11Device and Documentation Support
1. 11.1 Device Support
2. 11.2 Documentation Support
3. 11.3 Receiving Notification of Documentation Updates
4. 11.4 Community Resources

• PW|24

#### 8.2.2.9 Input Capacitance (CIN)

The input voltage in this design is 390 VDC, which is typically fed by the output of a PFC boost pre-regulator. It is typical to select input capacitance based on holdup and ripple requirements.

Note:

The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).

Calculate tank frequency using Equation 89:

Equation 89. Estimate the delay time using Equation 90:

Equation 90. The effective duty cycle clamp (DCLAMP) is calculated in Equation 91:

Equation 91. VDROP is the minimum input voltage where the converter can still maintain output regulation (see Equation 92). The converter’s input voltage would only drop down this low during a brownout or line-drop condition if this converter was following a PFC pre-regulator.

Equation 92. CIN was calculated in Equation 93 based on one line cycle of holdup:

Equation 93. Calculate the high-frequency input capacitor RMS current (ICINRMS) using Equation 94.

Equation 94.

To meet the input capacitance and RMS current requirements for this design, a 330-µF capacitor was chosen from Panasonic part number EETHC2W331EA:

CIN = 330 µF

This capacitor has a high frequency (ESRCIN) of 150 mΩ and is measured with an impedance analyzer at 200 kHz. ESRCIN = 0.150 Ω

Estimate the CIN power dissipation (PCIN) using Equation 95:

Equation 95. And recalculate the remaining power budget using Equation 96:

Equation 96. There is approximately 6.0 W that remains in the power budget for the current-sensing network, to bias the control device, and for all resistors supporting the control device.