SLUSDB2A August   2018  – December 2021 UCC28951

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Start-Up Protection Logic
      2. 7.3.2  Voltage Reference (VREF)
      3. 7.3.3  Error Amplifier (EA+, EA–, COMP)
      4. 7.3.4  Soft-Start and Enable (SS/EN)
      5. 7.3.5  Light-Load Power Saving Features
      6. 7.3.6  Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
      7. 7.3.7  Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
      8. 7.3.8  Minimum Pulse (TMIN)
      9. 7.3.9  Burst Mode
      10. 7.3.10 Switching Frequency Setting
      11. 7.3.11 Slope Compensation (RSUM)
      12. 7.3.12 Dynamic SR ON/OFF Control (DCM Mode)
      13. 7.3.13 Current Sensing (CS)
      14. 7.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
      15. 7.3.15 Synchronization (SYNC)
      16. 7.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
      17. 7.3.17 Supply Voltage (VDD)
      18. 7.3.18 Ground (GND)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select FETs QE and QF
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, R7, DA)
          1. 8.2.2.10.1 Voltage Loop Compensation Recommendation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

Operate the UCC28951 controller from a VDD rail within the limits given in the Section 6.3 section of this data sheet. To avoid the possibility that the controller might stop switching, do not allow the VDD to fall into the UVLO_FTH range. To minimize power dissipation in the controller, ensure that VDD is not unnecessarily high. Maintaining VDD at 12 V is a good compromise between these competing constraints. The gate drive outputs from the controller deliver large-current pulses into their loads. This indicates the need for a low-ESR decoupling capacitor to be connected as directly as possible between the VDD and GND terminals.

TI recommends ceramic capacitors with stable dielectric characteristics over temperature, such as X7R. Avoid capacitors which have a large drop in capacitance with applied DC voltage bias. For example, use a component that has a low-voltage co-efficient of capacitance. The recommended decoupling capacitance is 1 μF, X7R, with at least a 25-V rating with a 0.1-µF NPO capacitor in parallel.