SLUSEV2C June   2022  – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
        2. 9.2.2.2  Primary Magnetizing Inductance of the Flyback Transformer (LM)
        3. 9.2.2.3  Number of Turns of the Flyback Transformer Windings
        4. 9.2.2.4  Current Sense Resistors (R24, R25) and Current Limiting
        5. 9.2.2.5  Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
        6. 9.2.2.6  Primary-Side Current Stress and Input Capacitor Selection
        7. 9.2.2.7  Secondary-Side Current Stress and Output Capacitor Selection
        8. 9.2.2.8  VDD Capacitors (C12, C18)
        9. 9.2.2.9  Gate Drive Network (R14, R16, Q6)
        10. 9.2.2.10 VREF Capacitor (C18)
        11. 9.2.2.11 RT/CT Components (R12, C15)
        12. 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
        13. 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
        14. 9.2.2.14 Voltage Feedback Compensation
          1. 9.2.2.14.1 Power Stage Gain, Poles, and Zeroes
          2. 9.2.2.14.2 Compensation Components
          3. 9.2.2.14.3 Bode Plots and Stability Margins
          4. 9.2.2.14.4 Stability Measurements
      3. 9.2.3 Application Curves
    3. 9.3 PCB Layout Recommendations
      1. 9.3.1 PCB Layout Routing Examples
    4. 9.4 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.3 Application Curves

GUID-20221021-SS0I-S8PS-6DK8-ZRVNJDHGPMSB-low.png
VIN applied to VOUT ready in 266 ms
CH1: VIN at 10 V/DIV
CH2: VDD at 4 V/DIV
CH3: COMP at 2 V/DIV
CH4: VOUT at 4 V/DIV via differential probe
Figure 9-10 HV Startup at 50 VIN, 20 W
GUID-20221021-SS0I-WVPW-P2NF-SLZ99L7MRJVT-low.png
VDD capacitor hold-up time = 12.6 ms
VOUT rise time = 17.2 ms
CH2: VDD at 4 V/DIV
CH3: COMP at 2V/DIV
CH4: VOUT at 4 V/DIV via differential probe
Figure 9-12 VOUT Soft Starting at 50 VIN, 20 W
GUID-20221021-SS0I-HVL6-MXSK-C9LQ0WLXHSDX-low.png
VIN applied to VOUT ready in 224 ms
CH1: VIN at 200 V/DIV
CH2: VDD at 4 V/DIV
CH3: COMP at 2 V/DIV
CH4: VOUT at 4 V/DIV via differential probe
Figure 9-11 HV Startup at 800 VIN, 40 W
GUID-20221021-SS0I-NB0M-B70Z-WCTHSXJWKTLS-low.png
VDD capacitor hold-up time = 8.9 ms
VOUT rise time = 9.1 ms
CH2: VDD at 4 V/DIV
CH3: COMP at 2V/DIV
CH4: VOUT at 4 V/DIV via differential probe
Figure 9-13 VOUT Soft Starting at 800 VIN, 40 W
GUID-20221021-SS0I-92LF-RWG2-P3QHPT8GPHKX-low.png
Soft Start Overshoot = 1.2 %
CH4: VOUT at 1 V/DIV via differential probe
Figure 9-14 VOUT Overshoot at 50 VIN, 20W
GUID-20221021-SS0I-BZN6-XLM9-PH1TMSGTJGXM-low.png
Output Voltage Ripple = 298 mVPP
CH4: VOUT at 200 mV/DIV via differential probe
Figure 9-16 Output Voltage Ripple at 50 VIN, 20W
GUID-20221021-SS0I-GG9W-KPCJ-VBHS8B3GD9FW-low.png
Soft Start Overshoot = 2.4 %
CH4: VOUT at 1 V/DIV via differential probe
Figure 9-15 VOUT Overshoot at 800 VIN, 40 W
GUID-20221021-SS0I-RZT4-SJTR-RDCRGVVQDRVD-low.png
Output Voltage Ripple = 388 mVPP
CH4: VOUT at 200 mV/DIV via differential probe
Figure 9-17 Output Voltage Ripple at 800 VIN, 40 W
GUID-20221021-SS0I-T5C2-1LGK-XWNHZRC1ZWJC-low.png
fSW = 42.6 kHz, tON = 16.3 us, Duty Cycle = 69 %
CH1: VGATE at 5 V/DIV
CH2: RT/CT at 500 mV/DIV
CH3: COMP at 400 mV/DIV
Figure 9-18 PWM Switching at 50 VIN, 20 W
GUID-20221021-SS0I-DQ1Q-S9X9-NGKLXMBGPWRT-low.png
250 mA to 1.3 A to 250 mA
VMAX = 16.1 V, VMIN = 15.4 V, dV = 0.7 V
CH1: COMP at 50 mV/DIV
CH2: I_LOAD at 500 mA/DIV
CH4: VOUT at 600 mV/DIV via differential probe
Figure 9-20 Load Transient at 800 VIN, 1 A Step Change
GUID-20221021-SS0I-ZF26-49FF-XQMZHMMZP7WW-low.png
fSW = 42.3 kHz, tON = 1.4 us, Duty Cycle = 5.9 %
CH1: VGATE at 5 V/DIV
CH2: RT/CT at 500 mV/DIV
CH3: COMP at 400 mV/DIV
Figure 9-19 PWM Switching at 800 VIN, 40 W
GUID-20221021-SS0I-LLPB-PJ2Z-8TLZPLNSM8RM-low.png
250 mA to 2.7 A to 250 mA
VMAX = 16.1 V, VMIN = 15.1V, dV = 1.0 V
CH1: COMP at 50 mV/DIV
CH2: I_LOAD at 800 mA/DIV
CH4: VOUT at 600 mV/DIV via differential probe
Figure 9-21 Load Transient at 800 VIN, 2.5 A Step