SLUSEV2C June   2022  – March 2023 UCC28C50-Q1 , UCC28C51-Q1 , UCC28C52-Q1 , UCC28C53-Q1 , UCC28C54-Q1 , UCC28C55-Q1 , UCC28C56H-Q1 , UCC28C56L-Q1 , UCC28C57H-Q1 , UCC28C57L-Q1 , UCC28C58-Q1 , UCC28C59-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)
        2. 9.2.2.2  Primary Magnetizing Inductance of the Flyback Transformer (LM)
        3. 9.2.2.3  Number of Turns of the Flyback Transformer Windings
        4. 9.2.2.4  Current Sense Resistors (R24, R25) and Current Limiting
        5. 9.2.2.5  Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress
        6. 9.2.2.6  Primary-Side Current Stress and Input Capacitor Selection
        7. 9.2.2.7  Secondary-Side Current Stress and Output Capacitor Selection
        8. 9.2.2.8  VDD Capacitors (C12, C18)
        9. 9.2.2.9  Gate Drive Network (R14, R16, Q6)
        10. 9.2.2.10 VREF Capacitor (C18)
        11. 9.2.2.11 RT/CT Components (R12, C15)
        12. 9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)
        13. 9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope Compensation
        14. 9.2.2.14 Voltage Feedback Compensation
          1. 9.2.2.14.1 Power Stage Gain, Poles, and Zeroes
          2. 9.2.2.14.2 Compensation Components
          3. 9.2.2.14.3 Bode Plots and Stability Margins
          4. 9.2.2.14.4 Stability Measurements
      3. 9.2.3 Application Curves
    3. 9.3 PCB Layout Recommendations
      1. 9.3.1 PCB Layout Routing Examples
    4. 9.4 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
9.2.2.14.2 Compensation Components

To compensate a peak-current-mode controller it’s very common to use a Type-II compensator. The Type-II compensator introduces a pole at DC, a relatively low frequency zero (fZ,COMP), and a higher frequency pole (fP,COMP). The pole at DC forces the system to have high gain at very low frequency and zero stead-state error.

Figure 9-4 Type-II Compensation with an Error Amplifier

The low frequency zero is formed by R18 and C19

Equation 34. fZ,COMP=12×π×C19×R18

The higher frequency pole is formed by R18 and C20

Equation 35. fP,COMP=12×π×C20×R18

The mid-frequency gain of the compensator is given by

Equation 36. GCOMP=R18(R17+R19)

First, select a crossover frequency, 625 Hz. Then, use the frequency response of the plant (control-to-output) at low input voltage to determine how much gain the compensator must add to increase the crossover to the desired bandwidth. In Figure 9-5 the plant is measured to be -23.3 dB at 625 Hz. Therefore, the error amplifier must have a mid-frequency gain of 14.6 V/V.

Figure 9-5 Measuring the plant gain at the desired crossover frequency: -23 dB at 625 Hz

Choose (R17+R19) = 22.5 kΩ, and solve for R18

Equation 37. R18=GCOMP×R17+R19=14.6 V/V ×22.5kΩ=328kΩ

Select a standard value for R18, like 324 kΩ.

Now that we know R18, it’s fairly straightforward to set fZ,COMP = fPOLE and solve for C19

Equation 38. fZ,COMP=fPOLE=12×π×C19×324kΩ=17 Hz
Equation 39. C19=28nF

Likewise, set fP,COMP = fZERO and solve the following for C20

Equation 40. fP,COMP=fZERO=12×π×C20×324kΩ=4.8 kHz
Equation 41. C20=102pF

Finally, choose standard capacitor values, C19 = 22 nF and C20 = 100 pF. Notice that a slightly lower value was used for C19 than calculated. This was done to have a faster “reset” time during after a load transient response. If the complete loop is found to have too little phase margin then C19 can be increased at the cost of slower reset time.