The UCC39002 is an advanced, high-performance, low-cost load-share controller that provides all the necessary functions to parallel multiple independent power supplies and modules. The UCC39002 can easily parallel currently available and popular synchronous buck converters, such as those designed with the TPS40050 controller.
The UCC39002 features a high-gain and high-precision amplifier to measure the voltage across a low-value current sense resistor. Because the amplifier is fully uncommitted, the current sense gain is user programmable. The extremely low input offset voltage of the UCC39002 current sense amplifier makes it suitable to measure current information across a low value sense resistor. Furthermore, the input common mode range includes ground and the positive supply rail of the UCC39002 (VDD). Accordingly, the current sense resistor can be placed in the ground return path or in the positive output rail of the power supply VO as long as VO ≤ VDD. The current sense amplifier is not unity gain stable and must have a minimum gain of three.
This is a unity-gain buffer amplifier to provide separation between the load share bus voltage and the output of the current sense amplifier. The circuit implements an ideal diode with virtually 0-V forward voltage drop by placing the diode inside the feedback loop of the amplifier. The diode function is used to automatically establish the role of the master module in the system. The UCC39002 which is assigned to be the master uses the load share bus driver amplifier to copy its output current information on to the load share bus.
All slave units, with lower output current levels by definition, have this ideal diode reversed biased (VCSO < VLS). Consequently, the VCSO and VLS signals will be separated. That allows the error amplifier of the UCC39002 to compare its respective module’s output current to the master module’s output current and make the necessary corrections to achieve a balanced current distribution.
Since the bus is always driven by a single load share bus driver amplifier, the number of modules (n) are limited by the output current capability of the amplifier according to Equation 1:
The number of parallel units can be increased by reducing the full scale bus voltage, that is, by reducing the current sense gain.
The load share bus receiver amplifier is a unity-gain buffer monitoring the load share bus voltage. Its primary purpose is to ensure that the load share bus is not loaded by the internal impedances of the UCC39002. The LS pin is already internally compensated and has an internal 15-kHz filter. Adding external capacitance, including stray capacitance, must be avoided to maintain stability
As pictured in the block diagram, the UCC39002 employs a transconductance also called gM type error amplifier. The gM amplifier was chosen because it requires only one pin, the output to be accessible for compensation.
The purpose of the error amplifier is to compare the average, per module current level to the output current of the respective module controlled by the UCC39002. It is accommodated by connecting the buffered VLS voltage to its noninverting input and the VCSO signal to its inverting input. If the average per module current, represented by the load share bus is higher than the module’s own output current, an error signal will be developed across the compensation components connected between the EAO pin and ground. The error signal is than used by the adjust amplifier to make the necessary output voltage adjustments to ensure equal output currents among the parallel operated power supplies.
In case the UCC39002 assumes the role of the master load share controller in the system or it is used in conjunction with a stand alone power module, the measured current signal on VCSO is approximately equal to the VLS voltage. To avoid erroneous output voltage adjustment, the input of the error amplifier incorporates a typically 25-mV offset to ensure that the inverting input of the error amplifier is biased higher than the noninverting input. Consequently, when the two signals are equal, there will be no adjustment made and the initial output voltage set point is maintained.
A current proportional to the error voltage VEAO on pin 6 is sunk by the ADJ pin. This current flows through the adjust resistor RADJ and changes the output voltage of the module controlled by the UCC39002. The amplitude of the current is set by the 500-Ω internal resistor between ground and the emitter of the amplifier’s open collector output transistor according to Figure 2. The adjust current value is given in Equation 2:
At the master module VEAO is 0 V, thus the adjust current must be zero as well. This ensures that the output voltage of the master module remains at its initial output voltage set point at all times.
Furthermore, at insufficient bias level, during a fault or when the UCC39002 is disabled, the noninverting input of the adjust amplifier is pulled to ground to prevent erroneous adjustment of the module’s output voltage by the load share controller.
The two inputs of the current sense amplifier are also used for implementing an ENABLE function. During normal operation CS− = CS+ and the internal offset added between the CS− voltage and the inverting input of the enable comparator ensures that the UCC39002 is always enabled. By forcing the CS− pin approximately 0.5 V above the CS+ pin, the UCC39002 can be forced into a disable mode. While disabled, the UCC39002 disconnects itself from the load share bus and its adjust current is zero.
Accidentally, the load share bus might be shorted to ground or to the positive bias voltage of the UCC39002. These events might result in erroneous output voltage adjustment. For that reason, the load share bus is continuously monitored by a window comparator as shown in Figure 3.
The FAULT signal is handled by the start-up and adjust logic which pulls the noninverting input of the adjust amplifier low when the FAULT signal is asserted.
The start-up and adjust logic responds to unusual operating conditions during start up, fault and disable. Under these circumstances the information obtainable by the error amplifier of the UCC39002 is not sufficient to make the right output voltage adjustment, therefore the adjust amplifier is forced to certain known states. Similarly, the driver amplifier of UCC39002 is disabled during these conditions.
In the UCC39002 and UCC29002, during start-up, the load share driver amplifier is disabled by the disconnect switch and the adjust amplifier is forced to sink the maximum current through the adjust resistor. This operating mode ensures that the module controlled by the UCC39002 will be able to quickly engage in sharing the load current since its output will be adjusted to a sufficiently high voltage immediately at turnon. Both the load share driver and the adjust amplifiers revert to normal operation as soon as the measured current exceeds 80% of the average per module current level represented by the LS bus voltage. The UCC29002 and UCC29001 does not have this logic at start up. In this way, the UCC2900x does not adjust the output of the module to its maximum adjustment range at turn on and engages load sharing at more moderate rate.
In case of a fault shorting the load share bus to ground or to the bias of the UCC39002 the load share bus driver and the adjust amplifiers are disabled. The same action takes place when the UCC39002 is disabled using the CS+ and CS− pins or when the bias voltage is below the minimum operating voltage.
The UCC39002 is built on a 15-V, high-performance BiCMOS process. Therefore, the maximum voltage across the VDD and GND pins (pin 3 and 4 respectively) is limited to 15 V. The recommended maximum operating voltage is 13.5 V which corresponds to the tolerance of the on-board 14.2-V Zener clamp circuit. In case the bias voltage could exceed the 13.5-V limit, the UCC39002 should be powered through a current limiting resistor. The current into the VDD pin must be limited to 10 mA as listed in Absolute Maximum Ratings.
The bypass capacitor for VDD is also the compensation for the input active clamp of the device and, as such, must be placed as close to the device pins (VDD and GND) as possible, using a good-quality, low-ESL capacitor, including trace length. The device is optimized for a capacitor value of 0.1 µF to 1 µF.
The UCC39002 does not have an undervoltage lockout circuit. The bias OK comparator works as an enable function with a 4.375-V threshold. While VDD < 4.375 V the load share control functions are disabled. While this might be inconvenient for some low voltage applications it is necessary to ensure high accuracy. The load share accuracy is dependent on working with relatively large signal amplitudes on the load share bus. If the internal offsets, current sense error and ground potential difference between the UCC39002 controllers are comparable in amplitude to the load share bus voltage, they can cause significant current distribution error in the system. The maximum voltage on the load share bus is limited approximately 1.7 V below the bias voltage level (VDD) which would result in an unacceptably low load share bus amplitude therefore poor accuracy at low VDD levels. To circumvent this potential design problem, the UCC39002 does not operate below the above mentioned 4.375-V bias voltage threshold. If the system does not have a suitable bias voltage available to power the UCC39002, TI recommends using an inexpensive charge pump which can generate the bias voltage for all the UCC39002s in the load share system.
The maximum VDD of the UCC39002 is 15 V. For higher-voltage applications, use the application solution as recommended in Figure 5. A Zener clamp on the VDD pin is provided internally so the device can be powered from higher voltage rails using a minimum number of external components.
The CSA inputs must be adjusted so as to not exceed their absolute maximum voltage ratings.
The following is a practical step-by-step design procedure on how to use the UCC39002 to parallel power modules for load sharing.
The power modules to be paralleled must be equipped with true remote sense or access to the feedback divider of the module’s error amplifier.
A typical high side application for a single module is shown in Figure 6 and is repeated for each module to be paralleled.
In Figure 6, P1 represents the output voltage terminals of the module, S1 represents the remote sense terminals of the module, and a signal on the SB2 terminal will enable the disconnect feature of the device. The load share bus is the common bus between all of the paralleled load share controllers. VDD must be decoupled with a good-quality ceramic capacitor returned directly to GND.
This condition occurs if the load share bus is shorted high or low. Under this condition the device responds by pulling the inverting input of the adjust amplifier low. See Fault Protection for details.
During start up the load share driver amplifier is disabled and the adjust amplifier is forced to sink the maximum current through the adjust resistor. See Start-Up and Adjust Logic for details.