SLUS495I September   2001  – May 2016 UCC29002 , UCC39002

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Differential Current Sense Amplifier (CS+, CS−, CSO)
      2. 7.3.2  Load Share Bus Driver Amplifier (CSO)
      3. 7.3.3  Load Share Bus Receiver Amplifier (LS)
      4. 7.3.4  Error Amplifier (EAO)
      5. 7.3.5  Adjust Amplifier Output (ADJ)
      6. 7.3.6  Enable Function (CS+, CS−)
      7. 7.3.7  Fault Protection
      8. 7.3.8  Start-Up and Adjust Logic
      9. 7.3.9  Bias and Bias OK Circuit (VDD)
      10. 7.3.10 Paralleling the Power Modules
      11. 7.3.11 Measuring the Loop of the Modules
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fault
      2. 7.4.2 Start-Up
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 The Shunt Resistor
        2. 8.2.2.2 The CSA Gain
        3. 8.2.2.3 Determining RADJUST
        4. 8.2.2.4 Error Amplifier Compensation
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The bypass capacitor for VDD is also the compensation for the input active clamp of the device and, as such, must be placed as close to the device pins (VDD and GND) as possible, using a good-quality, low-ESL capacitor, including trace length.

10.2 Layout Example

UCC29002 UCC29002-1 UCC39002 Layout Example-1.gif Figure 11. Layout Example