SLUS504H SEPTEMBER   2002  – January 2016 UCC27321 , UCC27322 , UCC37321 , UCC37322

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Power Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
      3. 8.3.3 Source and Sink Capabilities during Miller Plateau
      4. 8.3.4 Enable
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-to-Output Configuration
        2. 9.2.2.2 Input Threshold Type
        3. 9.2.2.3 VDD Bias Supply Voltage
        4. 9.2.2.4 Peak Source and Sink Currents
        5. 9.2.2.5 Enable and Disable Function
        6. 9.2.2.6 Propagation Delay
        7. 9.2.2.7 Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Information
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Related Products
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
  • DGN|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN MAX UNIT
Supply voltage, VDD –0.3 16 V
Output current (OUT) DC, IOUT_DC 0.6 A
Input voltage (IN), VIN –0.3 6 V or VDD + 0.3(3) V
Enable voltage (ENBL) –0.3 6 V or VDD + 0.3(3) V
Power dissipation at TA = 25°C D package 650 mW
DGN package 3 W
P package 350 mW
Lead temperature (soldering, 10 s) 300 °C
Junction operating temperature, TJ –55 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating ConditionsRecommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
(3) Whichever is larger

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage, VDD 4.5 15 V

7.4 Thermal Information

THERMAL METRIC(1) UCC27322 UCC27321 UNIT
D (SOIC) P (PDIP) DGN (MSOP-PowerPAD)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 56.6 55.9 56.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.8 45.3 52.9 °C/W
RθJB Junction-to-board thermal resistance 32.6 32.6 32.7 °C/W
ψJT Junction-to-top characterization parameter 1.8 23.0 1.8 °C/W
ψJB Junction-to-board characterization parameter 32.3 32.5 32.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9 5.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

VDD = 4.5 V to 15 V, TA = –40°C to +105°C for UCC2732x, TA = 0°C to 70°C for UCC3732x, TA = TJ, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT (IN)
VIN_H, logic 1 input threshold 2 V
VIN_L, logic 0 input threshold 1 V
Input current 0 V ≤ VIN ≤ VDD –10 0 10 µA
OUTPUT (OUT)
Peak output current(1)(2) VDD = 14 V, 9 A
VOH, output high level VOH = VDD – VOUT, IOUT = –10 mA 150 300 mV
VOL, output low level IOUT = 10 mA 11 25 mV
Output resistance high(3) IOUT = –10 mA, VDD = 14 V 15 25 Ω
Output resistance low(3) IOUT = 10 mA, VDD = 14 V 1.1 2.2 Ω
Latch--up protection(1) 500 mA
OVERALL
IDD, static operating current UCC37321
UCC27321
IN = LOW, EN = LOW, VDD = 15 V 150 225 µA
IN = HIGH, EN = LOW, VDD = 15 V 440 650
IN = LOW, EN = HIGH, VDD = 15 V 370 550
IN = HIGH, EN = HIGH, VDD = 15 V 370 550
UCC37322
UCC27322
IN = LOW, EN = LOW, VDD = 15 V 150 225
IN = HIGH, EN = LOW, VDD = 15 V 450 650
IN = LOW, EN = HIGH, VDD = 15 V 75 125
IN = HIGH, EN = HIGH, VDD = 15 V 675 1000
ENABLE (ENBL)
VIN_H, high-level input voltage LOW to HIGH transition 1.7 2.2 2.7 V
VIN_L, low-level input voltage HIGH to LOW transition 1.1 1.6 2 V
Hysteresis 0.25 0.55 0.90
RENBL, enable impedance VDD = 14 V, ENBL = GND 75 100 135
(1) Ensured by design. Not tested in production.
(2) The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors.
(3) The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

7.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ENABLE (ENBL)
tD3, propagation delay time(1) CLOAD = 10 nF 60 90 ns
tD4, propagation delay time(1) CLOAD = 10 nF 60 90 ns
SWITCHING TIME(2)
tR, rise time (OUT) CLOAD = 10 nF 20 70 ns
tF, fall time (OUT) CLOAD = 10 nF 20 30 ns
tD1, propagation delay, IN rising (IN to OUT) CLOAD = 10 nF 25 70 ns
tD2, propagation delay, IN falling (IN to OUT) CLOAD = 10 nF 35 70 ns
(1) See Figure 2.
(2) See Figure 1 for switching waveforms.

7.7 Power Dissipation Ratings

PACKAGE SUFFIX θjc (°C/W) θja (°C/W) Power Rating
(mW)
TA = 70°C(1)
Derating Factor
Above
70°C (mW/°C)(1)
SOIC-8 D 42 84 to 160(2) 344 to 655(2) 6.25 to 11.9(2)
PDIP-8 P 49 110 500 9
MSOP PowerPAD-8 DGN 4.7 50 to 59 1370 17.1
(1) 125°C operating junction temperature is used for power rating calculations
(2) The range of values indicates the effect of the printed-circuit-board. These values are intended to give the system designer an indication of the best and worst case conditions. In general, the system designer should attempt to use larger traces on the printed-circuit-board where possible to spread the heat away form the device more effectively. For additional information on device temperature management, see the Packaging Information section of the Power Supply Control Products Data Book, (SLUD003).
UCC27321 UCC27322 UCC37321 UCC37322 switch_wave_invert_input_lus504.gif
The 20% and 80% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET transition through the Miller regions of operation.
Figure 1. Switching Waveforms for (a) Inverting Input to (b) Output Times
UCC27321 UCC27322 UCC37321 UCC37322 switch_wave_enable_lus504.gif
The 20% and 80% thresholds depict the dynamics of the BiPolar output devices that dominate the power MOSFET transition through the Miller regions of operation.
Figure 2. Switching Waveform for Enable to Output

7.8 Typical Characteristics

UCC27321 UCC27322 UCC37321 UCC37322 typ_fig5_lus504.gif
Figure 3. Input Current Idle vs Supply Voltage (UCCx7321)
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig7_lus504.gif
Figure 5. Input Current Idle vs Temperature (UCCx7321)
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig9_lus504.gif
Figure 7. Rise Time vs Supply Voltage
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig11_lus504.gif
Figure 9. Rise Time vs Load Capacitance
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig13_lus504.gif
Figure 11. tD1 Delay Time vs Supply Voltage
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig15_lus504.gif
Figure 13. tD1 Delay Time vs Load Capacitance
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig17_lus504.gif
Figure 15. Propagation Times vs Peak Input Voltage
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig19_lus504.gif
Figure 17. Enable Threshold and Hysteresis vs Temperature
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig21_lus504.gif
Figure 19. Output Behavior vs VDD (UCC37321)
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig23_lus504.gif
Figure 21. Output Behavior vs VDD (Inverting)
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig27_lus504.gif
Figure 23. Output Behavior vs VDD (Noninverting)
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig6_lus504.gif
Figure 4. Input Current Idle vs Supply Voltage (UCCx7322)
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig8_lus504.gif
Figure 6. Input Current Idle vs Temperature (UCCx7322)
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig10_lus504.gif
Figure 8. Fall Time vs Supply Voltage
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig12_lus504.gif
Figure 10. Fall Time vs Output Capacitance
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig14_lus504.gif
Figure 12. tD2 Delay Time vs Supply Voltage
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig16_lus504.gif
Figure 14. tD2 Delay Time vs Load Capacitance
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig18_lus504.gif
Figure 16. Input Threshold vs Temperature
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig20_lus504.gif
Figure 18. Enable Resistance vs Temperature
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig22_lus504.gif
Figure 20. Output Behavior vs VDD (UCC37321)
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig24_lus504.gif
Figure 22. Output Behavior vs VDD (Inverting)
UCC27321 UCC27322 UCC37321 UCC37322 typ_fig28_lus504.gif
Figure 24. Output Behavior vs VDD (Noninverting)