SLUS456F April   1999  – July 2018 UCC2808A-1 , UCC2808A-2 , UCC3808A-1 , UCC3808A-2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Pin Descriptions
        1. 7.3.1.1 COMP
        2. 7.3.1.2 CS
        3. 7.3.1.3 FB
        4. 7.3.1.4 GND
        5. 7.3.1.5 OUTA and OUTB
        6. 7.3.1.6 RC
        7. 7.3.1.7 VDD
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCC
      2. 7.4.2 Push-Pull or Half-Bridge Function
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TA = 0°C to 70°C for the UCC3808A-x and –40°C to +85°C for the UCC2808A-x, VDD = 10 V(1), 1-µF capacitor from VDD to GND, R = 22 kΩ, C = 330 pF, and TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OSCILLATOR
Oscillator frequency 175 194 213 kHz
Oscillator amplitude/VDD(2) 0.44 0.5 0.56 V/V
ERROR AMPLIFIER
Input voltage COMP = 2 V 1.95 2 2.05 V
Input bias current –1 1 µA
Open loop voltage gain 60 80 dB
COMP sink current FB = 2.2 V, COMP = 1 V 0.3 2.5 mA
COMP source current FB = 1.3 V, COMP = 3.5 V –0.2 –0.5 mA
PWM
Maximum duty cycle Measured at OUTA or OUTB 48% 49% 50%
Minimum duty cycle COMP = 0 V 0%
CURRENT SENSE
Gain(3) 1.9 2.2 2.5 V/V
Maximum input signal COMP = 5 V(4) 0.45 0.5 0.55 V
CS to output delay COMP = 3.5 V,
CS from 0 mV to 600 mV		 100 200 ns
CS source current –200 nA
CS sink current CS = 0.5 V, RC = 5.5 V(5) 5 10 mA
Over current threshold 0.7 0.75 0.8 V
COMP to CS offset CS = 0 V 0.35 0.8 1.2 V
OUTPUT
OUT low level I = 100 mA 0.5 1 V
OUT high level I = –50 mA, VDD – OUT 0.5 1 V
Rise time CL = 1 nF 25 60 ns
Fall time CL = 1 nF 25 60 ns
UNDERVOLTAGE LOCKOUT
Start threshold UCCx808A-1(1) 11.5 12.5 13.5 V
UCCx808A-2 4.1 4.3 4.5
Minimum operating voltage after start UCCx808A-1 7.6 8.3 9 V
UCCx808A-2 3.9 4.1 4.3
Hysteresis UCCx808A-1 3.5 4.2 5.1 V
UCCx808A-2 0.1 0.2 0.3
SOFT START
COMP rise time FB = 1.8 V, rise from 0.5 V to 4 V 3.5 20 ms
OVERALL
Start-up current VDD < start threshold 130 260 µA
Operating supply current FB = 0 V, CS = 0 V(1)(6) 1 2 mA
VDD zener shunt voltage IDD = 10 mA(7) 13 14 15 V
(1) For UCCx808A-1, set VDD above the start threshold before setting at 10 V.
(2) Measured at RC. Signal amplitude tracks VDD.
(3) Gain is defined by: A = ΔVCOMP / ΔVCS, 0 V ≤ VCS ≤ 0.4 V.
(4) Parameter measured at trip point of latch with FB at 0 V.
(5) The internal current sink on the CS pin is designed to discharge an external filter capacitor. It is not intended to be a DC sink path.
(6) Does not include current in the external oscillator network.
(7) Start threshold and Zener shunt threshold track one another.