SLUS157Q December   1999  – October 2019 UCC1895 , UCC2895 , UCC3895


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  ADS (Adaptive Delay Set)
      2. 7.3.2  CS (Current Sense)
      3. 7.3.3  CT (Oscillator Timing Capacitor)
      4. 7.3.4  DELAB and DELCD (Delay Programming Between Complementary Outputs)
      5. 7.3.5  EAOUT, EAP, and EAN (Error Amplifier)
      6. 7.3.6  OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
      7. 7.3.7  PGND (Power Ground)
      8. 7.3.8  RAMP (Inverting Input of the PWM Comparator)
      9. 7.3.9  REF (Voltage Reference)
      10. 7.3.10 RT (Oscillator Timing Resistor)
      11. 7.3.11 GND (Analog Ground)
      12. 7.3.12 SS/DISB (Soft Start/Disable)
      13. 7.3.13 SYNC (Oscillator Synchronization)
      14. 7.3.14 VDD (Chip Supply)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Power Loss Budget
        2.  Preliminary Transformer Calculations (T1)
        3.  QA, QB, QC, QD FET Selection
        4.  Selecting LS
        5.  Selecting Diodes DB and DC
        6.  Output Inductor Selection (LOUT)
        7.  Output Capacitance (COUT)
        8.  Select Rectifier Diodes
        9.  Input Capacitance (CIN)
        10. Current Sense Network (CT, RCS, RR, DA)
          1. Output Voltage Setpoint
          2. Voltage Loop Compensation
          3. Setting the Switching Frequency
          4. Soft Start
          5. Setting the Switching Delays
          6. Setting the Slope Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Current Sense Network (CT, RCS, RR, DA)

The CT chosen for this design has a turns ratio (CTRAT) of 100:1.

Equation 82. UCC1895 UCC2895 UCC3895 qu84_lua560.gif

Calculate nominal peak current (IP1) at VINMIN:

Peak primary current:

Equation 83. UCC1895 UCC2895 UCC3895 qu85_lua560.gif

The CS pin voltage where peak current limit will trip.

Equation 84. UCC1895 UCC2895 UCC3895 qu86_lua560.gif

Calculate current sense resistor (RCS) and leave 300 mV for slope compensation. Include a 1.1 factor for margin:

Equation 85. UCC1895 UCC2895 UCC3895 qu87_lua560.gif

Select a standard resistor for RCS:

Equation 86. UCC1895 UCC2895 UCC3895 qu88_lua560.gif

Estimate power loss for RCS:

Equation 87. UCC1895 UCC2895 UCC3895 qu89_lua560.gif

Calculate maximum reverse voltage (VDA) on DA:

Equation 88. UCC1895 UCC2895 UCC3895 qu90_lua560.gif

Estimate DA power loss (PDA):

Equation 89. UCC1895 UCC2895 UCC3895 qu91_lua560.gif

Calculate reset resistor RR:

Resistor RR is used to reset the current sense transformer CT.

Equation 90. UCC1895 UCC2895 UCC3895 eq_90_slus157.gif

Resistor RLF and capacitor CLF form a low pass filter for the current sense signal (Pin 15). For this design we chose the following values. This filter has a low frequency pole (fLFP) at 482 kHz. This should work for most applications but may be adjusted to suit individual layouts and EMI present in the design.

Equation 91. UCC1895 UCC2895 UCC3895 eq_91_slus157.gif
Equation 92. UCC1895 UCC2895 UCC3895 qu94_lua560.gif
Equation 93. UCC1895 UCC2895 UCC3895 eq_93_slus157.gif

The UCC3895 REF output (Pin 4) needs a high frequency bypass capacitor to filter out high frequency noise. The maximum amount of capacitance allowed is given in the Recommended Operating Conditions.

Equation 94. UCC1895 UCC2895 UCC3895 qu96_lua560.gif

The voltage amplifier reference voltage (Pin 2, EA+) can be set with a voltage divider (R1, R2), for this design example, the error amplifier reference voltage (V1) will be set to 2.5 V. Select a standard resistor value for R1 and then calculate resistor value R2.

UCC3895 reference voltage:

Equation 95. UCC1895 UCC2895 UCC3895 qu97_lua560.gif

Set voltage amplifier reference voltage:

Equation 96. UCC1895 UCC2895 UCC3895 qu98_lua560.gif
Equation 97. UCC1895 UCC2895 UCC3895 qu99_lua560.gif
Equation 98. UCC1895 UCC2895 UCC3895 qu100_lua560.gif

Voltage divider formed by resistor R3 and R4 are chosen to set the DC output voltage (VOUT) at Pin 3 (EA–).

Select a standard resistor for R3:

Equation 99. UCC1895 UCC2895 UCC3895 qu101_lua560.gif

Calculate R4:

Equation 100. UCC1895 UCC2895 UCC3895 qu102_lua560.gif

Then choose a standard resistor for R4:

Equation 101. UCC1895 UCC2895 UCC3895 qu103_lua560.gif