SLUS157Q December   1999  – October 2019 UCC1895 , UCC2895 , UCC3895


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  ADS (Adaptive Delay Set)
      2. 7.3.2  CS (Current Sense)
      3. 7.3.3  CT (Oscillator Timing Capacitor)
      4. 7.3.4  DELAB and DELCD (Delay Programming Between Complementary Outputs)
      5. 7.3.5  EAOUT, EAP, and EAN (Error Amplifier)
      6. 7.3.6  OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
      7. 7.3.7  PGND (Power Ground)
      8. 7.3.8  RAMP (Inverting Input of the PWM Comparator)
      9. 7.3.9  REF (Voltage Reference)
      10. 7.3.10 RT (Oscillator Timing Resistor)
      11. 7.3.11 GND (Analog Ground)
      12. 7.3.12 SS/DISB (Soft Start/Disable)
      13. 7.3.13 SYNC (Oscillator Synchronization)
      14. 7.3.14 VDD (Chip Supply)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Power Loss Budget
        2.  Preliminary Transformer Calculations (T1)
        3.  QA, QB, QC, QD FET Selection
        4.  Selecting LS
        5.  Selecting Diodes DB and DC
        6.  Output Inductor Selection (LOUT)
        7.  Output Capacitance (COUT)
        8.  Select Rectifier Diodes
        9.  Input Capacitance (CIN)
        10. Current Sense Network (CT, RCS, RR, DA)
          1. Output Voltage Setpoint
          2. Voltage Loop Compensation
          3. Setting the Switching Frequency
          4. Soft Start
          5. Setting the Switching Delays
          6. Setting the Slope Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Setting the Switching Delays

Higher power designs will benefit from the adaptive delays provided by the ADS pin but that feature is not used in this example. Setting RADSH = 0 Ω defeats the adaptive delay and a fixed value for tDELAB and tDELCD is used. If it is planned to use the adaptive delay feature then the resistor RADSL should be included in the layout but not populated until delay optimisation is being done on actual hardware.

UCC1895 UCC2895 UCC3895 figure_adaptive_delays.gifFigure 20. UCC3895 Adaptive Delays

We set the delay times as follows. The resonant frequency of the shim inductor LS with the stray capacitance at the switched node is given by:

Equation 112. UCC1895 UCC2895 UCC3895 qu_q_112_lus157.gif

Set the initial tABSET and tCDSET values to half the resonant period

Equation 113. UCC1895 UCC2895 UCC3895 qu_q_113_lus157.gif

The resistors RAB and RCD are given by a modified version of Equation 5 and Equation 6.

Equation 114. UCC1895 UCC2895 UCC3895 qu_q_114_lus157.gif

It is important to recognise that the delay times set by RAB and RCD are those measured at the device pins. Propagation delays mean that the delay times seen at the primary of the transformer will be different and this is the reason why the delays have to be optimised on actual hardware. Once the prototype is up and running it is recommended that you fine tune tABSET and tCDSET at light load. Refer to Figure 21 and Figure 22. It is easier to achieve ZVS at the drain of QD than at the drain of QA because the output inductor current reflected in the transformer primary is greater at QD and QC turn-off than it is at QA and QB turn-off.

UCC1895 UCC2895 UCC3895 fig5_lua560.gifFigure 21. tABSET to Achieve Valley Switching at Light Loads
UCC1895 UCC2895 UCC3895 fig6_lua560.gifFigure 22. tCDSET to Achieve Valley Switching at Light Loads