SLUSDV5B October 2019 – April 2020 UCC5304
Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge to output and it is defined as tVCCI+ to OUT for VCCI UVLO, which is 40 µs typically, and tVDD+ to OUT for VDD UVLO, which is 22 µs typically. It is recommended to allow proper delay margin after the driver VCCI and VDD bias supplies are ready before applying the PWM signal at the IN pin. Figure 18 and Figure 19 show the power-up UVLO delay timing diagram for VCCI and VDD.
If the IN pin is active before VCCI or VDD have crossed above their respective on thresholds, the output will not update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1µs delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to ensure safe operation during VCCI or VDD brownouts.