SLLSER8F June   2017  – January 2019 UCC5310 , UCC5320 , UCC5350 , UCC5390

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram (S, E, and M Versions)
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Function
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications for D Package
    7. 7.7  Insulation Specifications for DWV Package
    8. 7.8  Safety-Related Certifications For D Package
    9. 7.9  Safety-Related Certifications For DWV Package
    10. 7.10 Safety Limiting Values
    11. 7.11 Electrical Characteristics
    12. 7.12 Switching Characteristics
    13. 7.13 Insulation Characteristics Curves
    14. 7.14 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 8.1.1 CMTI Testing
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supply
      2. 9.3.2 Input Stage
      3. 9.3.3 Output Stage
      4. 9.3.4 Protection Features
        1. 9.3.4.1 Undervoltage Lockout (UVLO)
        2. 9.3.4.2 Active Pulldown
        3. 9.3.4.3 Short-Circuit Clamping
        4. 9.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 9.4 Device Functional Modes
      1. 9.4.1 ESD Structure
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing IN+ and IN– Input Filter
        2. 10.2.2.2 Gate-Driver Output Resistor
        3. 10.2.2.3 Estimate Gate-Driver Power Loss
        4. 10.2.2.4 Estimating Junction Temperature
      3. 10.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 10.2.3.1 Selecting a VCC1 Capacitor
        2. 10.2.3.2 Selecting a VCC2 Capacitor
        3. 10.2.3.3 Application Circuits With Output Stage Negative Bias
      4. 10.2.4 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Certifications
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CL = 100-pF, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCC1 Input supply quiescent current 1.67 2.4 mA
IVCC2 Output supply quiescent current 1.1 1.8 mA
SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VIT+(UVLO1) VCC1 Positive-going UVLO threshold voltage 2.6 2.8 V
VIT– (UVLO1) VCC1 Negative-going UVLO threshold voltage 2.4 2.5 V
Vhys(UVLO1) VCC1 UVLO threshold hysteresis 0.1 V
UCC5310MC, UCC5320SC,UCC5320EC,UCC5390SC,UCC5390EC, and UCC5350MC UVLO THRESHOLDS (12-V UVLO Version)
VIT+(UVLO2) VCC2 Positive-going UVLO threshold voltage 12 13 V
VIT–(UVLO2) VCC2 Negative-going UVLO threshold voltage 10.3 11 V
Vhys(UVLO2) VCC2 UVLO threshold voltage hysteresis 1 V
UCC5350SB UVLO THRESHOLD (8-V UVLO Version)
VIT+(UVLO2) VCC2 Positive-going UVLO threshold voltage 8.7 9.4 V
VIT–(UVLO2) VCC2 Negative-going UVLO threshold voltage 7.3 8.0 V
Vhys(UVLO2) VCC2 UVLO threshold voltage hysteresis 0.7 V
LOGIC I/O
VIT+(IN) Positive-going input threshold voltage (IN+, IN–) 0.55 × VCC1 0.7 × VCC1 V
VIT–(IN) Negative-going input threshold voltage (IN+, IN–) 0.3 × VCC1 0.45 × VCC1 V
Vhys(IN) Input hysteresis voltage (IN+, IN–) 0.1 × VCC1 V
IIH High-level input leakage at IN+ IN+ = VCC1 40 240 µA
IIL Low-level input leakage at IN– IN– = GND1 –240 –40 µA
IN– = GND1 – 5 V –310 –80
GATE DRIVER STAGE
VOH High-level output voltage (VCC2 - OUT) and
(VCC2 - OUTH)
IOUT = –20 mA 100 240 mV
VOL Low level output voltage (OUT and OUTL) UCC5320SC and UCC5320EC,
IN+ = low, IN– = high; IO = 20 mA
9.4 13 mV
UCC5310MC,
IN+ = low, IN– = high; IO = 20 mA
17 26
UCC5390SC and UCC5390EC,
IN+ = low, IN– = high; IO = 20 mA
2 3
UCC5350MC and UCC5350SB,
IN+ = low, IN– = high; IO = 20 mA
5 7
IOH Peak source current UCC5320SC and UCC5320EC,
IN+ = high, IN– = low
2.4 4.3 A
UCC5310MC, IN+ = high, IN– = low 2.4 4.3
UCC5390SC and UCC5390EC,
IN+ = high, IN– = low
10 17
UCC5350MC,
IN+ = high, IN– = low
5 10
UCC5350SB
IN+ = high, IN– = low
5 8.5
IOL Peak sink current UCC5320SC and UCC5320EC,
IN+ = low, IN– = high
2.2 4.4 A
UCC5310MC, IN+ = low, IN– = high 1.1 2.2
UCC5390SC and UCC5390EC,
IN+ = low, IN– = high
10 17
UCC5350MC,
IN+ = low, IN– = high
5 10
UCC5350SB
IN+ = low, IN– = high
5 10
ACTIVE MILLER CLAMP (UCC53xxM only)
VCLAMP Low-level clamp voltage UCC5310MC, ICLAMP = 20 mA 26 50 mV
UCC5350MC, ICLAMP = 20 mA 7 10
ICLAMP Clamp low-level current UCC5310MC, VCLAMP = VEE2 + 15 V 1.1 2.2 A
UCC5350MC, VCLAMP = VEE2 + 15 V 5 10
ICLAMP(L) Clamp low-level current for low output voltage UCC5310MC, VCLAMP = VEE2 + 2 V 0.7 1.5 A
UCC5350MC, VCLAMP = VEE2 + 2 V 5 10
VCLAMP-TH Clamp threshold voltage UCC5310MC and UCC5350MC 2.1 2.3 V
SHORT CIRCUIT CLAMPING
VCLP-OUT Clamping voltage
(VOUTH – VCC2 or VOUT –VCC2)
IN+ = high, IN– = low, tCLAMP = 10 µs,
IOUTH or IOUT= 500 mA
1 1.3 V
VCLP-OUT Clamping voltage
(VEE2 – VOUTL or VEE2 – VCLAMP or VEE2 – VOUT)
IN+ = low, IN– = high, tCLAMP = 10 µs,
ICLAMP or IOUTL = –500 mA
1.5 V
IN+ = low, IN– = high,
ICLAMP or IOUTL = –20 mA
0.9 1
ACTIVE PULLDOWN
VOUTSD Active pulldown voltage on OUTL, CLAMP, OUT IOUTL or IOUT = 0.1 × IOUTL(typ), VCC2 = open 1.8 2.5 V