SLLSER8F June   2017  – January 2019

PRODUCTION DATA.

1. Features
2. Applications
3. Description
4. Revision History
5. Device Comparison Table
6. Pin Configuration and Function
7. Specifications
8. Parameter Measurement Information
1. 8.1 Propagation Delay, Inverting, and Noninverting Configuration
9. Detailed Description
1. 9.1 Overview
2. 9.2 Functional Block Diagram
3. 9.3 Feature Description
1. 9.3.1 Power Supply
2. 9.3.2 Input Stage
3. 9.3.3 Output Stage
4. 9.3.4 Protection Features
4. 9.4 Device Functional Modes
10. 10Application and Implementation
1. 10.1 Application Information
2. 10.2 Typical Application
11. 11Power Supply Recommendations
12. 12Layout
13. 13Device and Documentation Support
14. 14Mechanical, Packaging, and Orderable Information

• D|8
• DWV|8

#### 10.2.2.2 Gate-Driver Output Resistor

The external gate-driver resistors, RG(ON) and RG(OFF) are used to:

1. Limit ringing caused by parasitic inductances and capacitances
2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
4. Reduce electromagnetic interference (EMI)

The output stage has a pullup structure consisting of a P-channel MOSFET and an N-channel MOSFET in parallel. The combined peak source current is 4.3 A for the UCC5320 family and 17 A for the UCC5390 family. Use Equation 1 to estimate the peak source current using the UCC5320S as an example.

Equation 1.

where

• RON is the external turnon resistance.
• RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will assume 0Ω for our example
• IOH is the peak source current which is the minimum value between 4.3 A, the gate-driver peak source current, and the calculated value based on the gate-drive loop resistance.

In this example, the peak source current is approximately 1.8 A as calculated in Equation 2.

Equation 2.

Similarly, use Equation 3 to calculate the peak sink current.

Equation 3.

where

• ROFF is the external turnoff resistance.
• IOL is the peak sink current which is the minimum value between 4.4 A, the gate-driver peak sink current, and the calculated value based on the gate-drive loop resistance.

In this example, the peak sink current is the minimum of Equation 4 and 4.4 A.

Equation 4.

NOTE

The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized. Conversely, the peak source and sink current is dominated by loop parasitics when the load capacitance (CISS) of the power transistor is very small (typically less than 1 nF) because the rising and falling time is too small and close to the parasitic ringing period.