SLLSER8F June   2017  – January 2019 UCC5310 , UCC5320 , UCC5350 , UCC5390

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram (S, E, and M Versions)
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Function
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications for D Package
    7. 7.7  Insulation Specifications for DWV Package
    8. 7.8  Safety-Related Certifications For D Package
    9. 7.9  Safety-Related Certifications For DWV Package
    10. 7.10 Safety Limiting Values
    11. 7.11 Electrical Characteristics
    12. 7.12 Switching Characteristics
    13. 7.13 Insulation Characteristics Curves
    14. 7.14 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 8.1.1 CMTI Testing
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supply
      2. 9.3.2 Input Stage
      3. 9.3.3 Output Stage
      4. 9.3.4 Protection Features
        1. 9.3.4.1 Undervoltage Lockout (UVLO)
        2. 9.3.4.2 Active Pulldown
        3. 9.3.4.3 Short-Circuit Clamping
        4. 9.3.4.4 Active Miller Clamp (UCC53x0M)
    4. 9.4 Device Functional Modes
      1. 9.4.1 ESD Structure
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Designing IN+ and IN– Input Filter
        2. 10.2.2.2 Gate-Driver Output Resistor
        3. 10.2.2.3 Estimate Gate-Driver Power Loss
        4. 10.2.2.4 Estimating Junction Temperature
      3. 10.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 10.2.3.1 Selecting a VCC1 Capacitor
        2. 10.2.3.2 Selecting a VCC2 Capacitor
        3. 10.2.3.3 Application Circuits With Output Stage Negative Bias
      4. 10.2.4 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 PCB Material
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Certifications
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Input Stage

The input pins (IN+ and IN–) of the UCC53x0 family are based on CMOS-compatible input-threshold logic that is completely isolated from the VCC2 supply voltage. The input pins are easy to drive with logic-level control signals (such as those from 3.3-V microcontrollers), because the UCC53x0 family has a typical high threshold (VIT+(IN)) of 0.55 × VCC1 and a typical low threshold of 0.45 × VCC1. A wide hysteresis (Vhys(IN)) of 0.1 × VCC1 makes for good noise immunity and stable operation. If any of the inputs are left open, 128 kΩ of internal pulldown resistance forces the IN+ pin low and 128 kΩ of internal resistance pulls IN– high. However, TI still recommends grounding an input or tying to VCC1 if it is not being used for improved noise immunity.

Because the input side of the UCC53x0 family is isolated from the output driver, the input signal amplitude can be larger or smaller than VCC2 provided that it does not exceed the recommended limit. This feature allows greater flexibility when integrating the gate-driver with control signal sources and allows the user to choose the most efficient VCC2 for any gate. However, the amplitude of any signal applied to IN+ or IN– must never be at a voltage higher than VCC1.