SLUSAP2I March   2012  – January 2017 UCD3138

PRODUCTION DATA.  

  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison Table
    1. 3.1 Product Family Comparison
    2. 3.2 Product Selection Matrix
  4. Pin Configuration and Functions
    1. 4.1 UCD3138RGC 64 QFN Pin Attributes
    2. 4.2 UCD3138RHA, UCD3138RMH and UCD3138RJA Pin Attributes
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing and Switching Characteristics
    7. 5.7 Power Supply Sequencing
    8. 5.8 Peripherals
      1. 5.8.1 Digital Power Peripherals (DPPs)
        1. 5.8.1.1 Front End
        2. 5.8.1.2 DPWM Module
        3. 5.8.1.3 DPWM Events
        4. 5.8.1.4 High Resolution DPWM
        5. 5.8.1.5 Oversampling
        6. 5.8.1.6 DPWM Interrupt Generation
        7. 5.8.1.7 DPWM Interrupt Scaling/Range
    9. 5.9 Typical Temperature Characteristics
  6. Detailed Description
    1. 6.1 Overview
    2. 6.2 ARM Processor
    3. 6.3 Memory
      1. 6.3.1 CPU Memory Map and Interrupts
      2. 6.3.2 Boot ROM
      3. 6.3.3 Customer Boot Program
      4. 6.3.4 Flash Management
    4. 6.4 System Module
      1. 6.4.1 Address Decoder (DEC)
      2. 6.4.2 Memory Management Controller (MMC)
      3. 6.4.3 System Management (SYS)
      4. 6.4.4 Central Interrupt Module (CIM)
    5. 6.5 Feature Description
      1. 6.5.1  Sync FET Ramp and IDE Calculation
      2. 6.5.2  Automatic Mode Switching
        1. 6.5.2.1 Phase Shifted Full Bridge Example
        2. 6.5.2.2 LLC Example
        3. 6.5.2.3 Mechanism for Automatic Mode Switching
      3. 6.5.3  DPWMC, Edge Generation, IntraMux
      4. 6.5.4  Filter
        1. 6.5.4.1 Loop Multiplexer
        2. 6.5.4.2 Fault Multiplexer
      5. 6.5.5  Communication Ports
        1. 6.5.5.1 SCI (UART) Serial Communication Interface
        2. 6.5.5.2 PMBUS
        3. 6.5.5.3 General Purpose ADC12
        4. 6.5.5.4 Timers
          1. 6.5.5.4.1 24-bit PWM Timer
          2. 6.5.5.4.2 16-Bit PWM Timers
          3. 6.5.5.4.3 Watchdog Timer
      6. 6.5.6  Miscellaneous Analog
      7. 6.5.7  Package ID Information
      8. 6.5.8  Brownout
      9. 6.5.9  Global I/O
      10. 6.5.10 Temperature Sensor Control
      11. 6.5.11 I/O Mux Control
      12. 6.5.12 Current Sharing Control
      13. 6.5.13 Temperature Reference
    6. 6.6 Device Functional Modes
      1. 6.6.1 Normal Mode
      2. 6.6.2 Phase Shifting
      3. 6.6.3 DPWM Multiple Output Mode
      4. 6.6.4 DPWM Resonant Mode
      5. 6.6.5 Triangular Mode
      6. 6.6.6 Leading Edge Mode
  7. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 7.2.2.2 DPWM Initialization for PSFB
        3. 7.2.2.3 DPWM Synchronization
        4. 7.2.2.4 Fixed Signals to Bridge
        5. 7.2.2.5 Dynamic Signals to Bridge
        6. 7.2.2.6 System Initialization for PCM
          1. 7.2.2.6.1 Use of Front Ends and Filters in PSFB
          2. 7.2.2.6.2 Peak Current Detection
          3. 7.2.2.6.3 Peak Current Mode (PCM)
      3. 7.2.3 Application Curves
  8. Power Supply Recommendations
    1. 8.1 Power Supply Decoupling and Bulk Capacitors
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Tools and Documentation
    2. 10.2 Documentation Support
      1. 10.2.1 References
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from H Revision (October 2016) to I Revision

  • Added updated Layout Guidelines section.Go
  • Added Layout Example images. Go

Changes from G Revision (September 2016) to H Revision

  • Added PACKAGE DRAWING column to the Device Information table. Go
  • Changed Note 2 from "Recommended for new 40-pin designs with advance BLR performance" to "Recommended for new 40-pin designs, optimized for improved performance under temperature cycling test for board level reliability (BLR)." Go
  • Deleted Figure 4-3 note, "These features help to improve solder-joint reliability". Go

Changes from F Revision (November 2013) to G Revision

  • Added Device and Documentation Support section and ESD Ratings table.Go
  • Changed document flow to match UCD3138A.Go
  • Added RJA package to Features and the Device Information table. Go
  • Added RJA package. Go
  • Added the RJA package to the Thermal Information table.Go

Changes from E Revision (August 2013) to F Revision

  • Changed Top Side Marking info from " 3138 " to " 3138RMH " in the Ordering Information table. Go

Changes from D Revision (August 2013) to E Revision

  • Added UCD3138RMH to Feature bulletGo
  • Added RMH package pinout drawingGo
  • Added RMH package thermal specificationsGo
  • Changed Global I/O registers ordered list, item 5 text from "Connecting pin/pins to high rail through internal pull up resistors." to "Configuring pin/pins as open drain or push-pull (Normal)"Go

Changes from C Revision (March 2013) to D Revision

  • Changed TOPT spec to TJ in Abs Max table with MAX temp of 150°CGo
  • Added BP18 Voltage vs Temperature graphicGo

Changes from B Revision (July 2012) to C Revision

  • Deleted "JTAG Debug Port" feature bulletGo
  • Deleted text string "JTAG debug" from Description section.Go
  • Added NOTE under Functional Block DiagramGo
  • Deleted "JTAG" option from Product Selection Matrix.Go
  • Added text to Pin 54 descriptionGo
  • Added text to Pin 35 descriptionGo
  • Added BP18 spec to Abs Max Ratings and Recommended Operating Conditions TablesGo
  • Deleted VDD specification from System Performance section of Electrical CharacteristicsGo
  • Added footnote to Table 5-1Go
  • Added text string regarding front-end 2 in the Front End section Go
  • Deleted text string reference to "JTAG port" in ARM Processor sectionGo
  • Changed illustration in IC Grounding and Layout Recommendations sectionGo
  • Changed text strings in Section 10.1.1.1Go
  • Added document to References listGo

Changes from A Revision (March 2012) to B Revision

  • Added Feature bulletsGo
  • Changed "Dual Edge Modulation" to "Triangular Modulation" in Features sectionGo
  • Changed "265 ksps" to "267 ksps" in Features section Go
  • Clarified number of UARTs in Feature sectionGo
  • Changed "FDPP" to "DDP" throughout.Go
  • Changed Total GPIO pin count for the UCD3138 40-pin device from "17" to "18" in the Product Selection Matrix table.Go
  • Changed "VREG" to "BP18" in conditions statement for Electrical CharacteristicsGo
  • Changed EAP – EAN Error voltage digital resolution MIN values for AFE = 3, AFE = 2, AFE = 1, AFE = 0 from 0.95, 1.90, 3.72, and 7.3 respectively; to, 0.8, 1.7, 3.55, and 6.90 respectively.Go
  • Changed conditions for VOL and VOH specifications in Electrical CharacteristicsGo
  • Added TWD specification to Electrical CharacteristicsGo
  • Changed "PWM" to "DPWM" in Section 5.8.1.2Go
  • Changed waveforms graphic for "Phase Shifted Full Bridge Example" for clarification Go
  • Added text to sectionSection 6.5.2.2 Go
  • Changed typical conversion speed from "268 ksps" to "267 ksps" in the General Purpose ADC12 section.Go
  • Added package ID information for the UCD3138RGC and UCD3138RHA devices.Go
  • Added bullet "AD02 has a special ESD protection mechanism that prevents the pin from pulling down the current-share bus if power is missing from the UCD3138" to Current Sharing Control.Go
  • Changed "PWMA" and "PWMB" to "DPWMA" and "DPWMB" in Section 6.6.1. Go
  • Added sub-bullet "The power pad of the driver IC should be tied to DGND" and changed capacitor value from "0.1 µF" to "4.7 µF" in Go
  • Changed " Mechanical Data" section to "References" sectionGo

Changes from * Revision (March 2012) to A Revision

  • Added Production Data statement to footnote and removed "Product Preview" bannerGo
  • Deleted table: Summary of Key Differences Between UCD3138x and UCD3138Go