SLUSAP2I March   2012  – January 2017 UCD3138


  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison Table
    1. 3.1 Product Family Comparison
    2. 3.2 Product Selection Matrix
  4. Pin Configuration and Functions
    1. 4.1 UCD3138RGC 64 QFN Pin Attributes
    2. 4.2 UCD3138RHA, UCD3138RMH and UCD3138RJA Pin Attributes
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing and Switching Characteristics
    7. 5.7 Power Supply Sequencing
    8. 5.8 Peripherals
      1. 5.8.1 Digital Power Peripherals (DPPs)
        1. Front End
        2. DPWM Module
        3. DPWM Events
        4. High Resolution DPWM
        5. Oversampling
        6. DPWM Interrupt Generation
        7. DPWM Interrupt Scaling/Range
    9. 5.9 Typical Temperature Characteristics
  6. Detailed Description
    1. 6.1 Overview
    2. 6.2 ARM Processor
    3. 6.3 Memory
      1. 6.3.1 CPU Memory Map and Interrupts
      2. 6.3.2 Boot ROM
      3. 6.3.3 Customer Boot Program
      4. 6.3.4 Flash Management
    4. 6.4 System Module
      1. 6.4.1 Address Decoder (DEC)
      2. 6.4.2 Memory Management Controller (MMC)
      3. 6.4.3 System Management (SYS)
      4. 6.4.4 Central Interrupt Module (CIM)
    5. 6.5 Feature Description
      1. 6.5.1  Sync FET Ramp and IDE Calculation
      2. 6.5.2  Automatic Mode Switching
        1. Phase Shifted Full Bridge Example
        2. LLC Example
        3. Mechanism for Automatic Mode Switching
      3. 6.5.3  DPWMC, Edge Generation, IntraMux
      4. 6.5.4  Filter
        1. Loop Multiplexer
        2. Fault Multiplexer
      5. 6.5.5  Communication Ports
        1. SCI (UART) Serial Communication Interface
        2. PMBUS
        3. General Purpose ADC12
        4. Timers
          1. 24-bit PWM Timer
          2. 16-Bit PWM Timers
          3. Watchdog Timer
      6. 6.5.6  Miscellaneous Analog
      7. 6.5.7  Package ID Information
      8. 6.5.8  Brownout
      9. 6.5.9  Global I/O
      10. 6.5.10 Temperature Sensor Control
      11. 6.5.11 I/O Mux Control
      12. 6.5.12 Current Sharing Control
      13. 6.5.13 Temperature Reference
    6. 6.6 Device Functional Modes
      1. 6.6.1 Normal Mode
      2. 6.6.2 Phase Shifting
      3. 6.6.3 DPWM Multiple Output Mode
      4. 6.6.4 DPWM Resonant Mode
      5. 6.6.5 Triangular Mode
      6. 6.6.6 Leading Edge Mode
  7. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. DPWM Initialization for PSFB
        3. DPWM Synchronization
        4. Fixed Signals to Bridge
        5. Dynamic Signals to Bridge
        6. System Initialization for PCM
          1. Use of Front Ends and Filters in PSFB
          2. Peak Current Detection
          3. Peak Current Mode (PCM)
      3. 7.2.3 Application Curves
  8. Power Supply Recommendations
    1. 8.1 Power Supply Decoupling and Bulk Capacitors
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. Tools and Documentation
    2. 10.2 Documentation Support
      1. 10.2.1 References
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
V33D V33D to DGND –0.3 3.8 V
V33DIO V33DIO to DGND –0.3 3.8 V
V33A V33A to AGND –0.3 3.8 V
BP18 BP18 to DGND –0.3 2.5 V
|DGND – AGND| Ground difference 0.3 V
All pins, excluding AGND(2) Voltage applied to any pin –0.3 3.8 V
TJ Junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Referenced to DGND

ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
V33D Digital power 3.0 3.3 3.6 V
V33DIO Digital I/O power 3.0 3.3 3.6
V33A Analog power 3.0 3.3 3.6 V
TJ Junction temperature –40 125 °C
BP18 1.8-V digital power 1.6 1.8 2.0 V

Thermal Information

RθJA Junction-to-ambient thermal resistance 25.1 31.8 31.0 30.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10.5 18.5 16.5 13.5 °C/W
RθJB Junction-to-board thermal resistance 4.6 6.8 6.3 4.9 °C/W
ψJT Junction-to-top characterization parameter 0.2 0.2 0.2 0.2 °C/W
ψJB Junction-to-board characterization parameter 4.6 6.7 6.3 4.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2 1.8 1.1 0.7 °C/W
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

V33A = V33D = V33DIO = 3.3 V; 1 μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
I33A Measured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled 6.3 mA
I33DIO All GPIO and communication pins are open 0.35 mA
I33D ROM program execution 60 mA
I33D Flash programming in ROM mode 70 mA
I33 The device is in ROM mode with all DPWMs enabled and switching at 2 MHz. The DPWMs are all unloaded. 100 mA
EAP – AGND –0.15 1.998 V
EAP – EAN –0.256 1.848 V
Typical error range AFE = 0 –256 248 mV
EAP – EAN Error voltage digital resolution AFE = 3 0.8 1 1.20 mV
AFE = 2 1.7 2 2.30 mV
AFE = 1 3.55 4 4.45 mV
AFE = 0 6.90 8 9.10 mV
REA Input impedance (See Figure 5-4) AGND reference 0.5
IOFFSET Input offset current (See Figure 5-4) –5 5 μA
EADC offset Input voltage = 0 V at AFE = 0 –2 2 LSB
Input voltage = 0 V at AFE = 1 –2.5 2.5 LSB
Input voltage = 0 V at AFE = 2 –3 -3 LSB
Input voltage = 0 V at AFE = 3 –4 4 LSB
Sample Rate 16 MHz
Analog Front End Amplifier Bandwidth 100 MHz
A0 Gain See Figure 5-5 1 V/V
Minimum output voltage 100 mV
DAC range 0 1.6 V
VREF DAC reference resolution 10 bit, No dithering enabled 1.56 mV
VREF DAC reference resolution With 4 bit dithering enabled 97.6 μV
INL –3.0 3.0 LSB
DNL Does not include MSB transition –2.1 1.6 LSB
DNL at MSB transition –1.4 LSB
DAC reference voltage 1.58 1.61 V
τ Settling Time From 10% to 90% 250 ns
IBIAS Bias current for PMBus address pins 9.5 10.5 μA
Measurement range for voltage monitoring 0 2.5 V
Internal ADC reference voltage –40°C to 125°C 2.475 2.500 2.525 V
Change in Internal ADC reference from 25°C reference voltage(1) –40°C to 25°C –0.4 mV
25°C to 85°C –1.8
25°C to 125°C –4.2
ADC12 INL integral nonlinearity(1) ADC_SAMPLINGSEL = 6 for all ADC12 data, 25 °C to 125 °C ±2.5 LSB
ADC12 DNL differential nonlinearity(1) –0.7/+2.5 LSB
ADC Zero Scale Error –7 7 mV
ADC Full Scale Error –35 35 mV
Input bias 2.5 V applied to pin 400 nA
Input leakage resistance(1) ADC_SAMPLINGSEL= 6 or 0 1
Input Capacitance(1) 10 pF
ADC single sample conversion time(1) ADC_SAMPLINGSEL= 6 or 0 3.9 μs
VOL Low-level output voltage(4) IOH = 4 mA, V33DIO = 3 V DGND
+ 0.25
VOH High-level output voltage (4) IOH = –4 mA, V33DIO = 3 V V33DIO – 0.6 V
VIH High-level input voltage V33DIO = 3 V 2.1 V
VIL Low-level input voltage V33DIO = 3 V 1.1 V
IOH Output sinking current 4 mA
IOL Output sourcing current –4 mA
TWD Watchdog time out range Total time is: TWD × (WDCTRL.PERIOD + 1) 14.6 17 20.5 ms
Time to disable DPWM output based on active FAULT pin signal High level on FAULT pin 70 ns
Processor master clock (MCLK) 31.25 MHz
tDelay Digital compensator delay(5) (1 clock = 32 ns) 6 clocks
t(reset) Pulse width needed at reset(1) 10 µs
Retention period of flash content (data retention and program) TJ = 25°C 100 years
Program time to erase one page or block in data flash or program flash 20 ms
Program time to write one word in data flash or program flash 20 µs
f(PCLK) Internal oscillator frequency 240 250 260 MHz
Sync-in/sync-out pulse width Sync pin 256 ns
Flash Read 1 MCLKs
Flash Write 20 μs
ISHARE Current share current source (See Figure 6-16) 238 259 μA
RSHARE Current share resistor (See Figure 6-16) 9.75 10.3
POWER ON RESET AND BROWN OUT (V33D pin, See Figure 5-3)
VGH Voltage good high 2.7 V
VGL Voltage good low 2.5 V
Vres Voltage at which IReset signal is valid 0.8 V
TPOR Time delay after power is good or RESET* relinquished 1 ms
Brownout Internal signal warning of brownout conditions 2.9 V
VTEMP Voltage range of sensor 1.46 2.44 V
Voltage resolution V/°C 5.9 mV/ºC
Temperature resolution °C per bit 0.1034 ºC/LSB
Accuracy(6)(7) –40°C to 125°C –10 ±5 10 ºC
Temperature range –40°C to 125°C –40 125 ºC
ITEMP Current draw of sensor when active 30 μA
TON Turn on time / settling time of sensor 100 μs
VAMB Ambient temperature Trimmed 25°C reading 1.85 V
DAC Reference DAC Range 0 2.5 V
Reference Voltage 2.478 2.5 2.513 V
Bits 7 bits
INL(6) –0.42 0.21 LSB
DNL(6) 0.06 0.12 LSB
Offset –5.5 19.5 mV
Time to disable DPWM output based on 0 V to 2.5 V step input on the analog comparator.(1) 150 ns
Reference DAC buffered output load(8) 0.5 1 mA
Buffer offset (–0.5 mA) 4.6 8.3 mV
Buffer offset (1.0 mA) –0.05 17 mV
As designed and characterized. Not 100% tested in production.
DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.
On the 40-pin package V33DIO is connected to V33D internally.
The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.
Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.
Characterized by design and not production tested.
Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.
Available from reference DACs for comparators D, E, F, and G.

Timing and Switching Characteristics

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and PMBus in Slave or Master mode are shown in Table 5-1, Figure 5-1, and Figure 5-2. The numbers in Table 5-1 arµe for 400 kHz operating frequency. However, the device supports all three speeds, standard (100 kHz), fast (400 kHz), and fast mode plus (1 MHz).

Table 5-1 PMBus/SMBus/I2C Timing

Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted)
fSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 100 1000 kHz
fI2C I2C operating frequency Slave mode, SCL 50% duty cycle 100 1000 kHz
t(BUF) Bus free time between start and stop(5) 1.3 µs
t(HD:STA) Hold time after (repeated) start(5) 0.6 µs
t(SU:STA) Repeated start setup time(5) 0.6 µs
t(SU:STO) Stop setup time(5) 0.6 µs
t(HD:DAT) Data hold time Receive mode 0 ns
t(SU:DAT) Data setup time 100 ns
t(TIMEOUT) Error signal/detect(1) 35 ms
t(LOW) Clock low period 1.3 µs
t(HIGH) Clock high period(2) 0.6 µs
t(LOW:SEXT) Cumulative clock low slave extend time(3) 25 ms
tf Clock/data fall time Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15) 20 + 0.1 Cb(4) 300 ns
tr Clock/data rise time Fall time tf = 0.9 VDD to (VILmax – 0.15) 20 + 0.1 Cb(4) 300 ns
Cb Total capacitance of one bus line 400 pF
The device times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
Cb (pF)
Fast mode, 400 kHz
UCD3138 I2C_tim_dia_lusap2.gif Figure 5-1 I2C/SMBus/PMBus Timing Diagram
UCD3138 bus_timing_lusap2.gif Figure 5-2 Bus Timing in Extended Mode

Power Supply Sequencing

UCD3138 POR_dwg_lusap2.gif Figure 5-3 Power-On Reset (POR) and Brown-Out Reset (BOR)

Table 5-2 Power-On Reset (POR) and Brown-Out Reset (BOR) Term Definitions

VGH This is the V33D threshold where the internal power is declared good. The UCD3138 comes out of reset when above this threshold.
VGL This is the V33D threshold where the internal power is declared bad. The device goes into reset when below this threshold.
Vres This is the V33D threshold where the internal reset signal is no longer valid. Below this threshold the device is in an indeterminate state.
IReset This is the internal reset signal. When low, the device is held in reset. This is equivalent to holding the reset pin on the IC high.
TPOR The time delay from when VGH is exceeded to when the device comes out of reset.
Brown out This is the V33D voltage threshold at which the device sets the brown out status bit. In addition an interrupt can be triggered if enabled.


Digital Power Peripherals (DPPs)

At the core of the UCD3138 controller are three DDPs. Each DPP can be configured to drive from one to eight DPWM outputs. Each DPP consists of:

  • Differential input error ADC (EADC) with sophisticated controls
  • Hardware accelerated digital 2-pole/2-zero PID based compensator
  • Digital PWM module with support for a variety of topologies

These can be connected in many different combinations, with multiple filters and DPWMs. They are capable of supporting functions like input voltage feed forward, current mode control, and constant current/constant power, and so forth. The simplest configuration is shown in the following figure:

UCD3138 fusion_dig_pwr_lusap2.gif

Front End

Figure 5-4 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range with 6 bits of resolution on the EADC output. The output of the Front End module is a 9-bit sign extended result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output could be either 1, 2, 4 or 8 LSBs. In addition Front End 0 has the ability to automatically select the AFE value such that the minimum resolution is maintained that still allows the voltage to fit within the range of the measurement. The EADC control logic receives the sample request from the DPWM module for initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the digital compensator for processing of the representative error. The set point DAC has 10 bits with an additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a variety of sources to facilitate things like soft start, nested loops, and so forth. Some additional features include the ability to change the polarity of the error measurement and an absolute value mode which automatically adds the DAC value to the error.

It is possible to operate the controller in a peak current mode control configuration; front-end 2 is recommended for implementing peak current mode control. In this mode topologies like the phase shifted full bridge converter can be controlled to maintain transformer flux balance. The internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified in Section 5.5.

UCD3138 REA_IOFFSET_lusap2.gif Figure 5-4 Input Stage of EADC Module
UCD3138 EADC_2_mod2_lusap2.gif Figure 5-5 Front End Module
(Front End 2 Recommended for Peak Current Mode Control)

DPWM Module

The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple DPWM modules within the UCD3138 system can be configured to support all key power topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM configurations.

The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width modulated outputs for the power stage switches. The compensator calculates the necessary duty ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON time. The resolution of the DPWM ON time is 250 psec.

Each DPWM module can be synchronized to another module or to an external sync signal. An input SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM modules—occur when the ramp timer crosses a programmed threshold. In this way the phase of the DPWM outputs for multiple power stages can be tightly controlled.

The DPWM logic is probably the most complex of the Digital Peripherals. It takes the output of the compensator and converts it into the correct DPWM output for several power supply topologies. It provides for programmable dead times and cycle adjustments for current balancing between phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers. Fault handling is covered in the Fault Mux section.

Each DPWM module supports the following features:

  • Dedicated 14 bit time-base with period and frequency control
  • Shadow period register for end of period updates.
  • Quad-event control registers (A and B, rising and falling) (Events 1 to 4)
    • Used for on/off DPWM duty ratio updates.
  • Phase control relative to other DPWM modules
  • Sample trigger placement for output voltage sensing at any point during the DPWM cycle.
  • Support for two independent edge placement DPWM outputs (same frequency or period setting)
  • Dead-time between DPWM A and B outputs
  • High Resolution capabilities – 250 ps
  • Pulse cycle adjustment of up to ±8.192 µs (32768 × 250 ps)
  • Active high/ active low output polarity selection
  • Provides events to trigger both CPU interrupts and start of ADC12 conversions.

DPWM Events

Each DPWM can control the following timing events:

  1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in relationship to the DPWM period. The programmed value set in the register should be one fourth of the value calculated based on the DPWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the circuitry runs at one fourth of the DPWM clock (PCLK = 250 MHz max). When this sample trigger count is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a CLA calculation, and a DPWM update. Oversampling can be set for 2, 4, or 8 times the sampling rate.
  2. Phase Trigger Count – count offset for slaving another DPWM (Multi-Phase/Interleaved operation).
  3. Period – low resolution switching period count. (count of PCLK cycles)
  4. Event 1 – count offset for rising DPWM A event. (PCLK cycles)
  5. Event 2 – DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
  6. Event 3 – DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
  7. Event 4 – DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
  8. Cycle Adjust – Constant offset for Event 2 and Event 4 adjustments.

Basic comparisons between the programmed registers and the DPWM counter can create the desired edge placements in the DPWM. High resolution edge capability is available on Events 2, 3, and 4.

Figure 5-6 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own registers, not by the filter output. In other words, the power supply control loop is not closed.

The Sample Trigger signals are used to trigger the front end to sample input signals. The Blanking signals are used to blank fault measurements during noisy events, such as FET turn on and turn off. Additional DPWM modes are described below.

UCD3138 mulit2_opn_loop_lusap2.gif Figure 5-6 Multi Mode Open Loop

High Resolution DPWM

Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM edges, the UCD3138 DPWM can generate waveforms with resolutions as small as 250 ps. This is 16× the resolution of the clock driving the DPWM module.

This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz each. The high resolution section of DPWM can be enabled or disabled, also the resolution can be defined in several steps between 4ns to 250ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN, HIRES_SCALE, and ALL_PHASE_CLK_ENA inside the DPWM Control register 1. See the Power Peripherals programmer’s manual for details.


The DPWM module has the capability to trigger an oversampling event by initiating the EADC to sample the error voltage. The default 00 configuration has the DPWM trigger the EADC once based on the sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The 01 setting triggers 2X oversampling, the 10 setting triggers 4X over sampling, and the 11 triggers oversampling at 8X.

DPWM Interrupt Generation

The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for sequence synchronization. Table 5-3 outlines the divide ratios that can be programmed.

DPWM Interrupt Scaling/Range

Table 5-3 DPWM Interrupt Divide Ratio

Interrupt Divide Setting Interrupt Divide Count Interrupt Divide Count (hex) Switching Period Frames (Assume 1-MHz Loop) Number of 32-MHz Processor Cycles
1 0 00 1 32
2 1 01 2 64
3 3 03 4 128
4 7 07 8 256
5 15 0F 16 512
6 31 1F 32 1024
7 47 2F 48 1536
8 63 3F 64 2048
9 79 4F 80 2560
10 95 5F 96 3072
11 127 7F 128 4096
12 159 9F 160 5120
13 191 BF 192 6144
14 223 DF 224 7168
15 255 FF 256 8192

Typical Temperature Characteristics

UCD3138 G005a_SLUSAP2.gif Figure 5-7 EADC LSB Size With 4X Gain (mV) vs Temperature
UCD3138 G006b_SLUSAP2.gif Figure 5-9 ADC12 Measurement Temperature Sensor Voltage vs Temperature
UCD3138 G002b_SLUSAP2.gif Figure 5-11 ADC12 Temperature Sensor Measurement Error vs Temperature
UCD3138 C001_SLUSAP2.png Figure 5-8 BP18 Voltage vs Temperature
UCD3138 G003b_SLUSAP2.gif Figure 5-10 ADC12 2.5-V Reference vs Temperature
UCD3138 G004b_SLUSAP2.gif Figure 5-12 UCD3138 Oscillator Frequency (2-MHz Reference, Divided Down from 250 MHz) vs Temperature