SLUSCA5B December   2015  – January 2017 UCD3138064A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Options
    1. 3.1 Device Comparison Table
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Diagrams
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 PMBus/SMBus/I2C Timing
    8. 5.8 Parametric Measurement Information
    9. 5.9 Typical Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 ARM Processor
    3. 6.3 Memory
    4. 6.4 Feature Description
      1. 6.4.1  System Module
        1. 6.4.1.1 Address Decoder (DEC)
        2. 6.4.1.2 Memory Management Controller (MMC)
        3. 6.4.1.3 System Management (SYS)
        4. 6.4.1.4 Central Interrupt Module (CIM)
      2. 6.4.2  Peripherals
        1. 6.4.2.1 Digital Power Peripherals
          1. 6.4.2.1.1 Front End
          2. 6.4.2.1.2 DPWM Module
          3. 6.4.2.1.3 DPWM Events
          4. 6.4.2.1.4 High Resolution DPWM
          5. 6.4.2.1.5 Over Sampling
          6. 6.4.2.1.6 DPWM Interrupt Generation
          7. 6.4.2.1.7 DPWM Interrupt Scaling/Range
      3. 6.4.3  Synchronous Rectifier Dead Time Optimization Peripheral
      4. 6.4.4  Automatic Mode Switching
        1. 6.4.4.1 Phase Shifted Full Bridge Example
        2. 6.4.4.2 LLC Example
        3. 6.4.4.3 Mechanism For Automatic Mode Switching
      5. 6.4.5  DPWMC, Edge Generation, IntraMux
      6. 6.4.6  Filter
        1. 6.4.6.1 Loop Multiplexer
        2. 6.4.6.2 Fault Multiplexer
      7. 6.4.7  Communication Ports
        1. 6.4.7.1 SCI (UART) Serial Communication Interface
        2. 6.4.7.2 PMBUS/I2C
        3. 6.4.7.3 SPI
      8. 6.4.8  Timers
        1. 6.4.8.1 24-Bit Timer
        2. 6.4.8.2 16-Bit PWM Timers
        3. 6.4.8.3 Watchdog Timer
      9. 6.4.9  General Purpose ADC12
      10. 6.4.10 Miscellaneous Analog
      11. 6.4.11 Brownout
      12. 6.4.12 Global I/O
      13. 6.4.13 Temperature Sensor Control
      14. 6.4.14 I/O Mux Control
      15. 6.4.15 Current Sharing Control
      16. 6.4.16 Temperature Reference
    5. 6.5 Device Functional Modes
      1. 6.5.1 DPWM Modes Of Operation
        1. 6.5.1.1 Normal Mode
        2. 6.5.1.2 Phase Shifting
        3. 6.5.1.3 DPWM Multiple Output Mode
        4. 6.5.1.4 DPWM Resonant Mode
      2. 6.5.2 Triangular Mode
      3. 6.5.3 Leading Edge Mode
    6. 6.6 Memory
      1. 6.6.1 Register Maps
        1. 6.6.1.1 CPU Memory Map and Interrupts
          1. 6.6.1.1.1 Memory Map (After Reset Operation)
          2. 6.6.1.1.2 Memory Map (Normal Operation)
          3. 6.6.1.1.3 Memory Map (System and Peripherals Blocks)
        2. 6.6.1.2 Boot ROM
        3. 6.6.1.3 Customer Boot Program
        4. 6.6.1.4 Flash Management
        5. 6.6.1.5 Synchronous Rectifier MOSFET Ramp and IDE Calculation
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 7.2.2.2 DPWM Initialization for PSFB
          1. 7.2.2.2.1 DPWM Synchronization
        3. 7.2.2.3 Fixed Signals to Bridge
        4. 7.2.2.4 Dynamic Signals to Bridge
        5. 7.2.2.5 System Initialization for PCM
          1. 7.2.2.5.1 Use of Front Ends and Filters in PSFB
          2. 7.2.2.5.2 Peak Current Detection
          3. 7.2.2.5.3 Peak Current Mode (PCM)
      3. 7.2.3 Application Curves
      4. 7.2.4 Power Supply Recommendations
      5. 7.2.5 Layout
        1. 7.2.5.1 Device Grounding and Layout Guidelines
        2. 7.2.5.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

4.1 Pin Diagrams

64-Pin QFN
RGC Package
Top View

UCD3138064A Pinout_revA_Cycl_64QFN_SLUSCA5.gif

Pin Functions

Pin Functions - 64 VQFN

PIN PRIMARY ASSIGNMENT ALTERNATE ASSIGNMENT CONFIGURABLE
AS A GPIO?
NUMBER NAME NO. 1 NO. 2 NO. 3 NO. 4 NO. 5
1 AGND Analog ground
2 AD13 12-bit ADC, Ch 13, comparator E, I-share DAC output
3 AD12 12-bit ADC, Ch 12
4 AD10 12-bit ADC, Ch 10
5 AD07 12-bit ADC, Ch 7, Connected to comparator F and reference to comparator G DAC output
6 AD06 12-bit ADC, Ch 6, Connected to comparator F DAC output
7 AD04 12-bit ADC, Ch 4, Connected to comparator D DAC output
8 AD03 12-bit ADC, Ch 3, Connected to comparator B and C
9 V33DIO Digital I/O 3.3V core supply, connected to V33D internally
10 DGND Digital ground
11 RESET Device Reset Input, active low
12 ADC_EXT ADC conversion external trigger input TCAP SYNC PWM0 Yes
13 SCI_RX0 SCI RX 0 DTC0 Yes
14 SCI_TX0 SCI TX 0 DTC1 Yes
15 PMBUS_CLK PMBUS Clock (Open Drain) SCI TX 0 Yes
16 PMBUS_DATA PMBus data (Open Drain) SCI RX 0 Yes
17 DPWM0A DPWM 0A output Yes
18 DPWM0B DPWM 0B output Yes
19 DPWM1A DPWM 1A output Yes
20 DPWM1B DPWM 1B output Yes
21 DPWM2A DPWM 2A output Yes
22 DPWM2B DPWM 2B output Yes
23 DPWM3A DPWM 3A output Yes
24 DPWM3B DPWM 3B output Yes
25 DGND Digital ground
26 SYNC DPWM Synchronize pin TCAP ADC_EXT_TRIG PWM0 DTC1 Yes
27 PMBUS_ALERT PMBus Alert (Open Drain) Yes
28 PMBUS_CTRL PMBus Control (Open Drain) Yes
29 SCI_TX1 SCI TX 1 PMBUS_ALERT Yes
30 SCI_RX1 SCI RX 1 PMBUS_CTRL Yes
31 PWM0 General purpose PWM 0 Yes
32 PWM1 General purpose PWM 1 Yes
33 DGND Digital ground
34 INT_EXT External Interrupt Yes
35 FAULT0 External fault input 0 SPI_CS I2C_DATA Yes
36 FAULT1 External fault input 1 SPI_CLK I2C_CLK Yes
37 TCK(1) JTAG TCK (for manufacturer test only) TCAP SYNC PWM0 DTC0 Yes
38 TDO(1) JTAG TDO (for manufacturer test only) SCI_TX0 PMBUS_ALERT FAULT0 SPI_MOSI DTC1 Yes
39 TDI(1) JTAG TDI (for manufacturer test only) SCI_RX0 PMBUS_CTRL FAULT1 SPI_MISO DTC0 Yes
40 TMS(1) JTAG TMS (for manufacturer test only) Yes
41 TCAP Timer capture input Yes
42 FAULT2 External fault input 2 Yes
43 FAULT3 External fault input 3 Yes
44 DGND Digital ground
45 V33DIO Digital I/O 3.3 V core supply, connected to V33D internally
46 BP18 1.8V Bypass
47 V33D Digital 3.3V core supply; V33DIO is connected to V33D internally
48 AGND Substrate analog ground
49 AGND Analog ground
50 EAP0 Channel #0, differential analog voltage, positive input
51 EAN0 Channel #0, differential analog voltage, negative input
52 EAP1 Channel #1, differential analog voltage, positive input
53 EAN1 Channel #1, differential analog voltage, negative input
54 EAP2 Channel #2, differential analog voltage, positive input
55 EAN2 Channel #2, differential analog voltage, negative input
56 AGND Analog ground
57 V33A Analog 3.3 V supply
58 AD00 12-bit ADC, Ch 0, Connected to current source
59 AD01 12-bit ADC, Ch 1, Connected to current source
60 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share
61 AD05 12-bit ADC, Ch 5
62 AD08 12-bit ADC, Ch 8
63 AD09 12-bit ADC, Ch 9
64 AD11 12-bit ADC, Ch 11
(1) Fusion Digital Power based debug tools are recommended instead of JTAG.