SLUSBZ8B June   2014  – February 2017 UCD3138128 , UCD3138A64

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Revision History
  4. Description
  5. Product Family Comparison
  6. Product Feature Overview
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  Handling Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Characteristics
    7. 8.7  PMBUS/SMBUS/IC Timing2
    8. 8.8  Timing Requirements
    9. 8.9  Power On Reset (POR) / Brown Out Detect (BOD)
    10. 8.10 Typical Clock Gating Power Savings
    11. 8.11 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 ARM Processor
      2. 9.1.2 Memory
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  System Module
        1. 9.3.1.1 Address Decoder (DEC)
        2. 9.3.1.2 Memory Management Controller (MMC)
        3. 9.3.1.3 System Management (SYS)
        4. 9.3.1.4 Central Interrupt Module (CIM)
      2. 9.3.2  Peripherals
        1. 9.3.2.1 Digital Power Peripherals
          1. 9.3.2.1.1 Front End
          2. 9.3.2.1.2 DPWM Module
          3. 9.3.2.1.3 DPWM Events
          4. 9.3.2.1.4 High Resolution DPWM
          5. 9.3.2.1.5 Over Sampling
          6. 9.3.2.1.6 DPWM Interrupt Generation
          7. 9.3.2.1.7 DPWM Interrupt Scaling/Range
      3. 9.3.3  Automatic Mode Switching
        1. 9.3.3.1 Phase Shifted Full Bridge Example
        2. 9.3.3.2 LLC Example
        3. 9.3.3.3 Mechanism For Automatic Mode Switching
      4. 9.3.4  DPWMC, Edge Generation, Intramux
      5. 9.3.5  Filter
        1. 9.3.5.1 Loop Multiplexer
        2. 9.3.5.2 Fault Multiplexer
      6. 9.3.6  Communication Ports
        1. 9.3.6.1 SCI (UART) Serial Communication Interface
        2. 9.3.6.2 PMBUS/I2C
        3. 9.3.6.3 SPI
      7. 9.3.7  Real Time Clock
      8. 9.3.8  Timers
        1. 9.3.8.1 24-Bit Timer
        2. 9.3.8.2 16-Bit PWM Timers
        3. 9.3.8.3 Watchdog Timer
      9. 9.3.9  General Purpose ADC12
      10. 9.3.10 Miscellaneous Analog
      11. 9.3.11 Brownout
      12. 9.3.12 Global I/O
      13. 9.3.13 Temperature Sensor Control
      14. 9.3.14 I/O Mux Control
      15. 9.3.15 Current Sharing Control
      16. 9.3.16 Temperature Reference
    4. 9.4 Device Functional Modes
      1. 9.4.1 DPWM Modes Of Operation
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 Phase Shifting
        3. 9.4.1.3 DPWM Multiple Output Mode
        4. 9.4.1.4 DPWM Resonant Mode
      2. 9.4.2 Triangular Mode
      3. 9.4.3 Leading Edge Mode
    5. 9.5 Register Maps
      1. 9.5.1 CPU Memory Map And Interrupts
        1. 9.5.1.1 Memory Map (After Reset Operation)
        2. 9.5.1.2 Memory Map (Normal Operation)
        3. 9.5.1.3 Memory Map (System And Peripherals Blocks)
      2. 9.5.2 Boot ROM
      3. 9.5.3 Customer Boot Program
      4. 9.5.4 Flash Management
    6. 9.6 Synchronous Rectifier MOSFET Ramp And IDE Calculation
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 10.2.2.2 DPWM Initialization for PSFB
        3. 10.2.2.3 DPWM Synchronization
        4. 10.2.2.4 Fixed Signals to Bridge
        5. 10.2.2.5 Dynamic Signals to Bridge
      3. 10.2.3 System Initialization for PCM
        1. 10.2.3.1 Use of Front Ends and Filters in PSFB
        2. 10.2.3.2 Peak Current Detection
        3. 10.2.3.3 Peak Current Mode (PCM)
      4. 10.2.4 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Device Grounding and Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Links
      2. 13.2.2 Related Documentation
        1. 13.2.2.1 References
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
MIN MAX
V33D V33D to DGND –0.3 3.8 V
V33DIO V33DIO to DGND –0.3 3.8 V
V33A V33A to AGND –0.3 3.8 V
BP18 BP18 to DGND -0.3 2.5 V
|DGND – AGND| Ground difference 0.3 V
RTC_IN_1_8/RSVD -0.3 3.0 V
All Pins, excluding AGND(2) Voltage applied to any pin –0.3 3.8 V
TOPT Junction Temperature –40 125 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Referenced to DGND

Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –55 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2000 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX UNIT
V33D Digital power 3.0 3.3 3.6 V
V33DIO Digital I/O power 3.0 3.3 3.6 V
V33A Analog power 3.0 3.3 3.6 V
BP18 1.8 V digital power 1.6 1.8 2.0 V
TJ Junction temperature -40 - 125 °C

Thermal Information

THERMAL METRIC(1) 80-PIN QFN UNIT
RθJA Junction-to-ambient thermal resistance 47.8 °C/W
RθJCtop Junction-to-case (top) thermal resistance 7.8
RθJB Junction-to-board thermal resistance 24.4
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter 24.0
RθJCbot Junction-to-case (bottom) thermal resistance N/A
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

Electrical Characteristics

V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENT
I33A(5) Measured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled 6.3 mA
I33DIO(5) All GPIO and communication pins are open 0.35 mA
I33D(5) ROM program execution 69 mA
I33 The device is in ROM mode with all DPWMs enabled and switching at 2 MHz. The DPWMs are all unloaded. 93 100 mA
ERROR ADC INPUTS EAP, EAN
EAP – AGND –0.15 1.998 V
EAP – EAN –0.256 1.848 V
Typical error range AFE = 0 –256 248 mV
EAP – EAN Error voltage digital resolution AFE = 3 0.8 1 1.20 mV
AFE = 2 1.7 2 2.30 mV
AFE = 1 3.55 4 4.45 mV
AFE = 0 6.90 8 9.10 mV
REA Input impedance (See Figure 9) AGND reference 0.5
IOFFSET Input offset current (See Figure 9) –5 5 μA
EADC Offset Input voltage = 0 V at AFE = 0 –16 16 mV
Input voltage = 0 V at AFE = 1 –10 10 mV
Input voltage = 0 V at AFE = 2 –6 -6 mV
Input voltage = 0 V at AFE = 3 –4 4 mV
Sample Rate 15.625 MHz
Analog Front End Amplifier Bandwidth 100 MHz
A0 Gain See Figure 10 1 V/V
Minimum output voltage 21 mV
EADC DAC
DAC range 0 1.6 V
VREF DAC reference resolution 10 bit, No dithering enabled 1.56 mV
VREF DAC reference resolution With 4 bit dithering enabled 97.6 μV
INL –1.5 1.5 LSB
DNL –1.0 2.1 LSB
DAC reference voltage 1.58 1.61 V
ADC12
IBIAS Bias current for PMBus address pins 9.5 10.5 μA
Measurement range for voltage monitoring 0 2.5 V
Internal ADC reference voltage –40°C to 125°C 2.475 2.500 2.53 V
Change in Internal ADC reference from 25°C reference voltage(5) –40°C to 25°C –0.7 mV
25°C to 125°C -6
ADC12 INL integral nonlinearity(5) ADC_SAMPLING_SEL = 6 for all ADC12 data, 25 °C to 125 °C -7.5/+2.9 LSB
ADC12 DNL differential nonlinearity(5) –0.7/+3.2 LSB
ADC Zero Scale Error –7 ±5 7 mV
ADC Full Scale Error –35 ±20 35 mV
Input bias 2.5 V applied to pin 200 nA
Input leakage resistance(5) ADC_SAMPLING_SEL= 6 or 0 1
Input Capacitance(5) 10 pF
DIGITAL INPUTS/OUTPUTS(1)(2)
VOL Low-level output voltage(3) IOH = 4 mA, V33DIO = 3 V DGND
+ 0.25
V
VOH High-level output voltage (3) IOH = –4 mA, V33DIO = 3 V V33DIO – 0.6 V
VIH High-level input voltage V33DIO = 3 V 2.1 V
VIL Low-level input voltage V33DIO = 3 V 1.1 V
IOH Output sinking current 4 mA
IOL Output sourcing current –4 mA
SYSTEM PERFORMANCE
Processor master clock (MCLK) 31.25 MHz
tDelay Digital filter delay(4) (1 clock = 32ns) 6 MCLKs
f(PCLK) Internal oscillator frequency 240 250 260 MHz
ISHARE Current share current source (See Figure 28) 238 259 μA
RSHARE Current share resistor (See Figure 28) 9.7 10.3
POWER ON RESET AND BROWN OUT (V33A pin, See Figure 3)
VGH Voltage good High 2.7 V
VGL Voltage good Low 2.5 V
Vres Voltage at which IReset signal is valid(5) 0.8 V
Brownout Internal signal warning of brownout conditions 2.9 V
TEMPERATURE SENSOR(5)
VTEMP Voltage range of sensor 1.46 2.44 V
Voltage resolution Volts/°C 6.3 mV/ºC
Temperature resolution Degree C per bit 0.0969 ºC/LSB
Accuracy(5)(6) -40°C to 125°C –10 ±5 10 ºC
Temperature range -40°C to 125°C –40 125 ºC
ITEMP Current draw of sensor when active 30 μA
VAMB Ambient temperature Trimmed 25°C reading 1.87 V
ANALOG COMPARATOR
DAC Reference DAC Range 0 2.5 V
Reference Voltage 2.478 2.5 2.513 V
Bits 7 bits
INL(5) –0.42 0.21 LSB
DNL(5) 0.06 0.12 LSB
Offset –5.5 19.5 mV
Reference DAC buffered output load(7) 0.5 1 mA
Buffer offset (-0.5 mA) 8.3 mV
Buffer offset (1.0 mA) 17 mV
RTC INTERFACE
fRTC RTC external input frequency 10 MHz
DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.
On the 40 pin package V33DIO is connected to V33D internally.
The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH.
Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.
Characterized by design and not production tested.
Ambient temperature offset value from the TEMPSENCTRL register should be used to meet accuracy.
Available from reference DACs for comparators D, E, F and G.

Timing Characteristics

V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
EADC DAC
t Settling Time From 10% to 90% 250 ns
ADC12
ADC single sample conversion time(2) ADC_SAMPLING_SEL= 6 or 0 3.9 μs
SYSTEM PERFORMANCE
TWD Watchdog time out resolution Total time is: TWD x (WDCTRL.PERIOD+1) 10.5 13.3 17 ms
Time to disable DPWM output based on active FAULT pin signal High level on FAULT pin 66 ns
Flash Read 1 MCLKs
tDelay Digital filter delay(1) (1 clock = 32ns) 6 MCLKs
Retention period of flash content (data retention and program) TJ = 25°C 100 years
Program time to erase one page or block in data flash or program flash 20 ms
Program time to write one word in program flash 50 µs
Program time to write one word in data flash 40 µs
Sync-in/sync-out pulse width Sync pin 256 ns
POWER ON RESET AND BROWN OUT (V33A pin, See Figure 3)
tPOR Time delay after Power is good or RESET* relinquished 1 ms
tEXC1 The time it takes from the device to exit a reset state and begin executing the boot flash.(2) IRESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state. 0.5 ms
tEXC2 The time it takes from the device to exit a reset state and begin executing program flash bank 0 (32 kB).(2) IRESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state. 3 ms
tEXCT The time it takes from the device to exit a reset state and begin executing the total program flash (64 kB).(2) IRESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state. 6 ms
TEMPERATURE SENSOR(2)
tON Turn on time / settling time of sensor 100 μs
ANALOG COMPARATOR
Bits 7 bits
INL(2) –0.42 0.21 LSB
DNL(2) 0.06 0.12 LSB
Time to disable DPWM output based on 0 V to 2.5 V step input on the analog comparator.(2) 90 150 ns
Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.
Characterized by design and not production tested.

PMBUS/SMBUS/IC Timing2

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and PMBus in Slave or Master mode are shown in the Timing Requirements, Figure 1, and Figure 2. The numbers in the Timing Requirements are for 400 kHz operating frequency. However, the device supports two speeds, standard (100 kHz) and fast (400 kHz).

Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted)
fSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 100 400 kHz
fI2C I2C operating frequency Slave mode, SCL 50% duty cycle 100 400 kHz
t(BUF) Bus free time between start and stop(5) 1.3 µs
t(HD:STA) Hold time after (repeated) start(5) 0.6 µs
t(SU:STA) Repeated start setup time(5) 0.6 µs
t(SU:STO) Stop setup time(5) 0.6 µs
t(HD:DAT) Data hold time Receive mode 0 ns
t(SU:DAT) Data setup time 100 ns
t(TIMEOUT) Error signal/detect(1) 35 ms
t(LOW) Clock low period 1.3 µs
t(HIGH) Clock high period(2) 35 ms
t(LOW:SEXT) Cumulative clock low slave extend time(3) 25 ms
tf Clock/data fall time Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15) 20 + 0.1 Cb(4) 300 ns
tr Clock/data rise time Fall time tf = 0.9 VDD to (VILmax – 0.15) 20 + 0.1 Cb(4) 300 ns
Cb Total capacitance of one bus line 400 pF
The device times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
Cb (pF)
Fast mode, 400 kHz
UCD3138128 UCD3138A64 I2C_tim_dia_lusap2.gif Figure 1. IC/SMBUS/PMBUS Timing Diagram2
UCD3138128 UCD3138A64 bus_timing_lusap2.gif Figure 2. Bus Timing In Extended Mode

Power On Reset (POR) / Brown Out Detect (BOD)

UCD3138128 UCD3138A64 POR_BOR_slusbz8.gif Figure 3. Power On Reset (POR) / Brown Out Reset (BOR)
VGH – This is the V33A threshold where the internal power is declared good. The UCD3138x comes out of reset when above this threshold.
VGL – This is the V33A threshold where the internal power is declared bad. The device goes into reset when below this threshold.
Vres This is the V33A threshold where the internal reset signal is no longer valid. Below this threshold the device is in an indeterminate state.
IReset This is the internal reset signal. When low, the device is held in reset. This is equivalent to holding the reset pin on the IC low.
tPOR The time delay from when VGH is exceeded to when the device comes out of reset.
Brown Out – This is the V33A voltage threshold at which the device sets the brown out status bit. In addition an interrupt can be triggered if enabled.

Typical Clock Gating Power Savings

UCD3138128 UCD3138A64 UCD3138064_clock_gating_pwer_savings3_SLUSB72.gif

The CLKGATECTRL register provides control bits that can enable or disable the clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.

By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled in order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current consumption of the device. The power savings chart displays the power savings per module. For example there are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved.

Typical Characteristics

UCD3138128 UCD3138A64 G005a_SLUSBL8.gif
Figure 4. EADC LSB Size With 4x Gain (Mv) vs. Temperature
UCD3138128 UCD3138A64 G003b_SLUSBL8.gif
Figure 6. ADC12 2.5-V Reference vs. Temperature
UCD3138128 UCD3138A64 G004c_SLUSBL8.gif
Figure 8. Oscillator Frequency (2MHz Reference, Divided Down From 250MHz) vs. Temperature
UCD3138128 UCD3138A64 G006b_SLUSBL8.gif
Figure 5. ADC12 Measurement Temperature Sensor Voltage vs. Temperature
UCD3138128 UCD3138A64 G002b_SLUSBL8.gif
Figure 7. ADC12 Temperature Sensor Measurement Error vs. Temperature