SLVSDD4C September   2016  – March 2020 UCD90160A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Rail Configuration
      2. 7.3.2 TI Fusion GUI
      3. 7.3.3 PMBus Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Supply Sequencing
        1. 7.4.1.1 Turn-on Sequencing
        2. 7.4.1.2 Turn-off Sequencing
        3. 7.4.1.3 Sequencing Configuration Options
      2. 7.4.2  Pin-Selected Rail States
      3. 7.4.3  Voltage Monitoring
      4. 7.4.4  Fault Responses and Alert Processing
      5. 7.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 7.4.6  GPIOs
      7. 7.4.7  GPO Control
      8. 7.4.8  GPO Dependencies
        1. 7.4.8.1 GPO Delays
        2. 7.4.8.2 State Machine Mode Enable
      9. 7.4.9  GPI Special Functions
        1. 7.4.9.1 Fault Shutdown Rails
        2. 7.4.9.2 Configured as Sequencing Debug Pin
        3. 7.4.9.3 Configured as Fault Pin
        4. 7.4.9.4 Cold Boot Mode Enable
      10. 7.4.10 Power Supply Enables
      11. 7.4.11 Cascading Multiple Devices
      12. 7.4.12 PWM Outputs
        1. 7.4.12.1 FPWM1-8
        2. 7.4.12.2 PWM1-4
      13. 7.4.13 Programmable Multiphase PWMs
      14. 7.4.14 Margining
        1. 7.4.14.1 Open-Loop Margining
        2. 7.4.14.2 Closed-Loop Margining
      15. 7.4.15 System Reset Signal
      16. 7.4.16 Watch Dog Timer
      17. 7.4.17 Run Time Clock
      18. 7.4.18 Data and Error Logging to Flash Memory
      19. 7.4.19 Brownout Function
      20. 7.4.20 PMBus Address Selection
      21. 7.4.21 Device Reset
    5. 7.5 Programming
      1. 7.5.1 Device Configuration and Programming
        1. 7.5.1.1 Full Configuration Update While in Normal Mode
      2. 7.5.2 JTAG Interface
      3. 7.5.3 Internal Fault Management and Memory Error Correction (ECC)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Estimating ADC Reporting Accuracy
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1 Design Requirements

The TRST pin must have a 10-kΩ pulldown resistor to ground and the RESET pin must have a 10-kΩ pullup resistor to V33D and a 1-nF decoupling capacitor to ground. The components must be placed as close to the RESET pin as possible.

Depending on application environment, the PMBus signal integrity may be compromised at times. This causes the UCD90160A to receive incorrect PMBus commands. In a particular case, if (D9h) ROM_MODE command is erroneously received by a UCD90160A device, it causes the device to enter ROM mode, in this mode the device does not function unless Fusion Digital Power Designer software is connected to the device. To avoid such occurrences in a running system, it is suggested to enable Packet Error Checking (PEC) in the PMBus host. The UCD90160A automatically detects and works with PMBus hosts, both with and without PEC enabled.

The fault log in UCD90160A is checksum protected. After new log entries are written into the fault log, the checksum is updated accordingly. After each device reset, UCD90160A re-calculates the fault log checksum and compares it with the existing checksum. If the two checksums are not the same, the device determines the fault log as corrupted and erases the fault log as a result.

In the event that the V33D power is dropped before the device finishes writing the fault log, the checksum is not updated correctly, thus the fault log is erased at the next power-up. The result is that no new faults are logged.

Such an event usually happens when the main power of the board drops and no standby power can stay alive for V33D. If such a scenario can be anticipated in an application, it is strongly suggested to use the brown-out function and circuit as described in the Brownout Function section.

When a pair of FPWM pin are configured as both Rail Enable and PWM(either margining or general purpose PWM) functions, there would be glitches on the pin configured as rail enable when device is out of reset and under initialization, which may impact the connected power rail. It is not recommended to have such configuration.

PMBus commands(system file, project file, PMBus write script file) method is not recommended for the production programming because GPIO pins may have unexpected behaviors which can disable rails that provide power to device. Data flash hex file or data flash script file shall be used for production programming because GPIO pins are under controlled state.

It is mandatory that the V33D power shall be stable and no device reset shall be fired during the device programming. Data flash may be corrupted if failed to follow these rules.

When a pair of FPWM pins are both used for margining, after device is out of reset, the even FPWM pin may output some pulse which is up to the configured duty cycle and frequency. These pulses may cause unexpected behaviors on the margining rail if that rail is regulated before UCD is out of reset. It is recommended to use the even FPWM pin to margin rails that are directly controlled by the device.

Glitch filter on the GPI fault response may not work as expected to filter the glitch. A external glitch filter circuit is required if a noise GPI input is present.

Ignore input during delay feature on the LGPO may latch the given LGPO output if other LGPOs are required to process during the delay period.

WARNING

Do not use the RESET pin to power cycle the rails. Instead, use the PMBus_CNTRL pin as described in the Power Supply Sequencing section; or, use the Pin-Selected Rail States function described in the Pin-Selected Rail States section.