SLVSDD7A September   2016  – February 2019 UCD9090A


  1. Features
  2. Applications
  3. Description
    1.     Typical Application Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C/Smbus/PMBus Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TI Fusion GUI
      2. 7.3.2 PMBus Interface
      3. 7.3.3 Rail Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Supply Sequencing
        1. Turn-On Sequencing
        2. Turn-Off Sequencing
        3. Sequencing Configuration Options
      2. 7.4.2  Pin-Selected Rail States
      3. 7.4.3  Monitoring
        1. Voltage Monitoring
        2. Current Monitoring
        3. Remote Temperature Monitoring and Internal Temperature Sensor
        4. Temperature by Host Input
      4. 7.4.4  Fault Responses and Alert Processing
      5. 7.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 7.4.6  GPIOs
      7. 7.4.7  GPO Control
      8. 7.4.8  GPO Dependencies
        1. GPO Delays
        2. State Machine Mode Enable
      9. 7.4.9  GPI Special Functions
        1. Fault Shutdown Rails
        2. Configured as Sequencing Debug Pin
        3. Configured as Fault Pin
        4. Cold Boot Mode Enable
      10. 7.4.10 Power Supply Enables
      11. 7.4.11 Cascading Multiple Devices
      12. 7.4.12 PWM Outputs
        1. FPWM1-8
        2. PWM1-2
      13. 7.4.13 Programmable Multiphase PWMs
      14. 7.4.14 Margining
        1. Open-Loop Margining
        2. Closed-Loop Margining
      15. 7.4.15 Run Time Clock
      16. 7.4.16 System Reset Signal
      17. 7.4.17 Watch Dog Timer
      18. 7.4.18 Data and Error Logging to Flash Memory
      19. 7.4.19 Brownout Function
      20. 7.4.20 PMBus Address Selection
      21. 7.4.21 Device Reset
      22. 7.4.22 JTAG Interface
      23. 7.4.23 Internal Fault Management and Memory Error Correction (ECC)
    5. 7.5 Programming
      1. 7.5.1 Full Configuration Update While in Normal Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Estimating ADC Reporting Accuracy
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Cascading Multiple Devices

A GPIO pin can be used to coordinate multiple controllers by using it as a power good-output from one device and connecting it to the PMBus_CNTRL input pin of another. This imposes a master/slave relationship among multiple devices. During startup, the slave controllers initiate their start sequences after the master has completed its start sequence and all rails have reached regulation voltages. During shutdown, as soon as the master starts to sequence-off, it sends the shut-down signal to its slaves.

A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple controllers, but it does not enforce interdependency between rails within a single controller.

Another method to cascade multiple devices is to connect the power-good output of the first device to a MON pin of the second device; connect the power-good output of the second device to a MON pin of the third device, and so on. Optionally, connect the power-good output of the last device to a MON pin of the first device. The rails controlled by a device have dependency on the previous device’s power-good output. This way, the rails controlled by multiple devices can be sequenced. Also, the de-assertion of a power-good output can trigger a UV fault of the next device. The UV fault response can be configured to shut down other rails controlled by the same device. This way, when one rail has fault shutdown, other rails controlled by other devices can be shut down accordingly.

The PMBus specification implies that the power-good signal is active when ALL the rails in a controller are regulating at their programmed voltage. The UCD9090A allows GPIOs to be configured to respond to a desired subset of power-good signals.

Multiple UCD9090A devices can also work together and coordinate when faults happen with a fault pin connection. One GPI pin can be configured as a Fault pin. The Fault pin is connected to a Fault Bus. Each Fault Bus is pulled up to 3.3 V by a 10-kΩ resistor. All the UCD9090A devices on the same Fault Bus are informed of the same fault condition. An example of Fault Pin connections is shown in Figure 24.

UCD9090A faultpincon_slvsdd7.gifFigure 24. Fault Pin Connection