SLVSDD7A September   2016  – February 2019 UCD9090A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Typical Application Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C/Smbus/PMBus Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TI Fusion GUI
      2. 7.3.2 PMBus Interface
      3. 7.3.3 Rail Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Supply Sequencing
        1. 7.4.1.1 Turn-On Sequencing
        2. 7.4.1.2 Turn-Off Sequencing
        3. 7.4.1.3 Sequencing Configuration Options
      2. 7.4.2  Pin-Selected Rail States
      3. 7.4.3  Monitoring
        1. 7.4.3.1 Voltage Monitoring
        2. 7.4.3.2 Current Monitoring
        3. 7.4.3.3 Remote Temperature Monitoring and Internal Temperature Sensor
        4. 7.4.3.4 Temperature by Host Input
      4. 7.4.4  Fault Responses and Alert Processing
      5. 7.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 7.4.6  GPIOs
      7. 7.4.7  GPO Control
      8. 7.4.8  GPO Dependencies
        1. 7.4.8.1 GPO Delays
        2. 7.4.8.2 State Machine Mode Enable
      9. 7.4.9  GPI Special Functions
        1. 7.4.9.1 Fault Shutdown Rails
        2. 7.4.9.2 Configured as Sequencing Debug Pin
        3. 7.4.9.3 Configured as Fault Pin
        4. 7.4.9.4 Cold Boot Mode Enable
      10. 7.4.10 Power Supply Enables
      11. 7.4.11 Cascading Multiple Devices
      12. 7.4.12 PWM Outputs
        1. 7.4.12.1 FPWM1-8
        2. 7.4.12.2 PWM1-2
      13. 7.4.13 Programmable Multiphase PWMs
      14. 7.4.14 Margining
        1. 7.4.14.1 Open-Loop Margining
        2. 7.4.14.2 Closed-Loop Margining
      15. 7.4.15 Run Time Clock
      16. 7.4.16 System Reset Signal
      17. 7.4.17 Watch Dog Timer
      18. 7.4.18 Data and Error Logging to Flash Memory
      19. 7.4.19 Brownout Function
      20. 7.4.20 PMBus Address Selection
      21. 7.4.21 Device Reset
      22. 7.4.22 JTAG Interface
      23. 7.4.23 Internal Fault Management and Memory Error Correction (ECC)
    5. 7.5 Programming
      1. 7.5.1 Full Configuration Update While in Normal Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Estimating ADC Reporting Accuracy
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Design Requirements

  1. The TRST pin must have a 10-kΩ pulldown resistor to ground.
  2. The RESET pin should have a 10-kΩ pullup resistor to V33D and a 1-nF decoupling capacitor to ground. The components should be placed as close to the RESET pin as possible.
  3. Depending on application environment, the PMBus signal integrity may be compromised at times. This will cause the UCD9090A to receive incorrect PMBus commands. In a particular case, if (D9h) ROM_MODE command is erroneously received by a UCD9090A device, it will cause the device to enter ROM mode, in which mode the device will not function unless Fusion GUI is connected to the device. To avoid such accidents in a running system, it is suggested to enable Packet Error Checking (PEC) in the PMBus host. UCD9090A can automatically detect and work with PMBus hosts both with and without PEC enabled.
  4. The fault log in UCD9090A is checksum protected. After new log entries are written into the fault log, the checksum will be updated accordingly. After each device reset, UCD9090A recalculates the fault log checksum and compare it with the existing checksum. If the two checksums are not the same, the device will deem the fault log as corrupted and will erase the fault log as a result.
    In the event that the V33D power is dropped before the device finish writing the fault log, the checksum will not be updated correctly, thus the fault log will be erased at the next power-up. The results is no new faults logged. Such an event usually happens when the main power of the board drops and no standby power can stay alive for V33D. If such a scenario can be anticipated in an application, it is strongly suggested to use the brown-out function and circuit as described in the previous section.
  5. Do not use the RESET pin to power cycle the rails. Instead, use the PMBus_CNTRL pin as described in Power Supply Sequencing, or use Pin-Selected Rail States function described in Pin-Selected Rail States.
  6. When a pair of FPWM pins are configured as both Rail Enable and PWM (either margining or general purpose PWM) functions, there can be glitches on the pin that is configured as rail enable when the device is out of reset and under initialization. These glitches may impact the connected power rail. It is not recommended to have such a configuration.
  7. PMBus commands (project file, PMBus write script file) method is not recommended for the production programming because GPIO pins may have unexpected behaviors which can disable rails that provide power to device. Data flash hex file or data flash script file shall be used for production programming because GPIO pins are under controlled state.
  8. It is mandatory that the V33D power shall be stable and no device reset shall be fired during the device programming. Data flash may be corrupted if failed to follow these rules.
  9. When a pair of FPWM pins are both used for margining, after device is out of reset, the even FPWM pin may output some pulse which is up to the configured duty cycle and frequency. These pulses may cause unexpected behaviors on the margining rail if that rail is regulated before UCD is out of reset. It is recommended to use the even FPWM pin to margin rails that are directly controlled by the device.