SLVSDD7A September 2016 – February 2019 UCD9090A
Each GPIO can be configured as a rail-enable pin with either active-low or active-high polarity. Output mode options include open-drain or push-pull outputs that can be actively driven to 3.3 V or ground. During reset, the GPIO pins are high-impedance except for FPWM/GPIO pins 17–24, which are driven low. External pulldown or pullup resistors can be tied to the enable pins to hold the power supplies off during reset. The UCD9090A can support a maximum of 10 enable pins.
GPIO pins that have FPWM capability (pins 10-17) should only be used as power supply enable signals if the signal is active high.