SLVSDD7A September   2016  – February 2019 UCD9090A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Typical Application Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C/Smbus/PMBus Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TI Fusion GUI
      2. 7.3.2 PMBus Interface
      3. 7.3.3 Rail Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Supply Sequencing
        1. 7.4.1.1 Turn-On Sequencing
        2. 7.4.1.2 Turn-Off Sequencing
        3. 7.4.1.3 Sequencing Configuration Options
      2. 7.4.2  Pin-Selected Rail States
      3. 7.4.3  Monitoring
        1. 7.4.3.1 Voltage Monitoring
        2. 7.4.3.2 Current Monitoring
        3. 7.4.3.3 Remote Temperature Monitoring and Internal Temperature Sensor
        4. 7.4.3.4 Temperature by Host Input
      4. 7.4.4  Fault Responses and Alert Processing
      5. 7.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 7.4.6  GPIOs
      7. 7.4.7  GPO Control
      8. 7.4.8  GPO Dependencies
        1. 7.4.8.1 GPO Delays
        2. 7.4.8.2 State Machine Mode Enable
      9. 7.4.9  GPI Special Functions
        1. 7.4.9.1 Fault Shutdown Rails
        2. 7.4.9.2 Configured as Sequencing Debug Pin
        3. 7.4.9.3 Configured as Fault Pin
        4. 7.4.9.4 Cold Boot Mode Enable
      10. 7.4.10 Power Supply Enables
      11. 7.4.11 Cascading Multiple Devices
      12. 7.4.12 PWM Outputs
        1. 7.4.12.1 FPWM1-8
        2. 7.4.12.2 PWM1-2
      13. 7.4.13 Programmable Multiphase PWMs
      14. 7.4.14 Margining
        1. 7.4.14.1 Open-Loop Margining
        2. 7.4.14.2 Closed-Loop Margining
      15. 7.4.15 Run Time Clock
      16. 7.4.16 System Reset Signal
      17. 7.4.17 Watch Dog Timer
      18. 7.4.18 Data and Error Logging to Flash Memory
      19. 7.4.19 Brownout Function
      20. 7.4.20 PMBus Address Selection
      21. 7.4.21 Device Reset
      22. 7.4.22 JTAG Interface
      23. 7.4.23 Internal Fault Management and Memory Error Correction (ECC)
    5. 7.5 Programming
      1. 7.5.1 Full Configuration Update While in Normal Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Estimating ADC Reporting Accuracy
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Voltage Monitoring

Up to 11 voltages can be monitored using the analog input pins. The input voltage range is 0 V–2.5 V for all MONx inputs except MON11 (pin 37) which has a range of 0.2V–2.5V. Any voltage between 0 V and 0.2 V on this pin is read as 0.2 V. External resistors can be used to attenuate voltages higher than 2.5 V.

The ADC operates continuously, requiring 3.89 μs to convert a single analog input. Each rail is sampled by the sequencing and monitoring algorithm every 400 μs. The maximum source impedance of any sampled voltage should be less than 4 kΩ. The source impedance limit is particularly important when a resistor-divider network is used to lower the voltage applied to the analog input pins.

MON1 - MON6 can be configured using digital hardware comparators, which can be used to achieve faster fault responses. Each hardware comparator has four thresholds (two UV (Fault and Warning) and two OV (Fault and Warning)). The hardware comparators respond to UV or OV conditions in about 80 μs (faster than 400 µs for the ADC inputs) and can be used to disable rails or assert GPOs. The only fault response available for the hardware comparators is to shut down immediately.

An internal 2.5-V reference is used by the ADC. The ADC reference has a tolerance of ±0.5% between 0°C and 125°C and a tolerance of ±1% between –40°C and 125°C. An external voltage divider is required for monitoring voltages higher than 2.5 V. The nominal rail voltage and the external scale factor can be entered into the Fusion GUI and are used to report the actual voltage being monitored instead of the ADC input voltage. The nominal voltage is used to set the range and precision of the reported voltage according to Table 3.

UCD9090A MonitorBlock_slvsdd7.gifFigure 12. Voltage Monitoring Block Diagram

Table 3. Voltage Range and Resolution

VOLTAGE RANGE (V) RESOLUTION (mV)
0 to 127.99609 3.90625
0 to 63.99805 1.95313
0 to 31.99902 0.97656
0 to 15.99951 0.48824
0 to 7.99976 0.24414
0 to 3.99988 0.12207
0 to 1.99994 0.06104
0 to 0.99997 0.03052

Although the monitor results can be reported with a resolution of about 15 μV, the real conversion resolution of 610 μV is fixed by the 2.5-V reference and the 12-bit ADC.