SWRS170I August   2014  – October 2017 WL1807MOD , WL1837MOD


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Attributes
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  External Digital Slow Clock Requirements
    5. 5.5  Thermal Resistance Characteristics for MOC 100-Pin Package
    6. 5.6  WLAN Performance: 2.4-GHz Receiver Characteristics
    7. 5.7  WLAN Performance: 2.4-GHz Transmitter Power
    8. 5.8  WLAN Performance: 5-GHz Receiver Characteristics
    9. 5.9  WLAN Performance: 5-GHz Transmitter Power
    10. 5.10 WLAN Performance: Currents
    11. 5.11 Bluetooth Performance: BR, EDR Receiver Characteristics—In-Band Signals
    12. 5.12 Bluetooth Performance: Transmitter, BR
    13. 5.13 Bluetooth Performance: Transmitter, EDR
    14. 5.14 Bluetooth Performance: Modulation, BR
    15. 5.15 Bluetooth Performance: Modulation, EDR
    16. 5.16 Bluetooth low energy Performance: Receiver Characteristics - In-Band Signals
    17. 5.17 Bluetooth low energy Performance: Transmitter Characteristics
    18. 5.18 Bluetooth low energy Performance: Modulation Characteristics
    19. 5.19 Bluetooth BR and EDR Dynamic Currents
    20. 5.20 Bluetooth low energy Currents
    21. 5.21 Timing and Switching Characteristics
      1. 5.21.1 Power Management
        1. Block Diagram - Internal DC-DCs
      2. 5.21.2 Power-Up and Shut-Down States
      3. 5.21.3 Chip Top-level Power-Up Sequence
      4. 5.21.4 WLAN Power-Up Sequence
      5. 5.21.5 Bluetooth-Bluetooth low energy Power-Up Sequence
      6. 5.21.6 WLAN SDIO Transport Layer
        1. SDIO Timing Specifications
        2. SDIO Switching Characteristics - High Rate
      7. 5.21.7 HCI UART Shared-Transport Layers for All Functional Blocks (Except WLAN)
        1. UART 4-Wire Interface - H4
      8. 5.21.8 Bluetooth Codec-PCM (Audio) Timing Specifications
  6. 6Detailed Description
    1. 6.1 WLAN Features
    2. 6.2 Bluetooth Features
    3. 6.3 Bluetooth low energy Features
    4. 6.4 Device Certification
      1. 6.4.1 FCC Certification and Statement
      2. 6.4.2 Innovation, Science, and Economic Development Canada (ISED)
      3. 6.4.3 ETSI/CE
      4. 6.4.4 MIC Certification
    5. 6.5 Module Markings
    6. 6.6 Test Grades
    7. 6.7 End Product Labeling
    8. 6.8 Manual Information to the End User
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
      1. 7.1.1 Typical Application - WL1837MOD Reference Design
      2. 7.1.2 Design Recommendations
      3. 7.1.3 RF Trace and Antenna Layout Recommendations
      4. 7.1.4 Module Layout Recommendations
      5. 7.1.5 Thermal Board Recommendations
      6. 7.1.6 Baking and SMT Recommendations
        1. Baking Recommendations
        2. SMT Recommendations
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. Tools and Software
      3. 8.1.3 Device Support Nomenclature
    2. 8.2 Related Links
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 TI Module Mechanical Outline
    2. 9.2 Tape and Reel Information
      1. 9.2.1 Tape and Reel Specification
      2. 9.2.2 Packing Specification
        1. Reel Box
        2. Shipping Box
    3. 9.3 Packaging Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • MOC|100
Thermal pad, mechanical data (Package|Pins)

Applications, Implementation, and Layout


Information in the following Applications section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

Typical Application – WL1837MOD Reference Design

Figure 7-1 shows the TI WL1837MODGI reference design.

WL1807MOD WL1837MOD WL1837MODGI-REF-SCH_150120.gif Figure 7-1 TI Module Reference Schematics

Table 7-1 lists the bill materials (BOM).

Table 7-1 Bill of Materials

1 WL1837 Wi-Fi / Bluetooth module WL1837MODGI 13.4 × 13.3 × 2.0 mm U1 1 TI
2 XOSC 3225 / 32.768 kHz / 1.8 V / ±50 ppm 7XZ3200005 3.2 × 2.5 × 1.0 mm OSC1 1 TXC
3 ANT / Chip / 2.4 GHz and 5 GHz(1) W3006 10.0 × 3.2 × 1.5 mm ANT1, ANT2 2 Pulse
4 Mini-RF header receptacle U.FL-R-SMT-1 (10) 3.0 × 2.6 × 1.25 mm J5, J6 2 Hirose
5 Inductor 0402 / 1.3 nH / ±0.1 nH / SMD LQP15MN1N3B02 0402 L1 1 Murata
6 Inductor 0402 / 1.8 nH / ±0.1 nH / SMD LQP15MN1N8B02 0402 L3 1 Murata
7 Inductor 0402 / 2.2 nH / ±0.1 nH / SMD LQP15MN2N2B02 0402 L4 1 Murata
8 Capacitor 0402 / 1 pF/ 50 V / C0G / ±0.1 pF GJM1555C1H1R0BB01 0402 C13 1 Murata
9 Capacitor 0402 / 2.4 pF / 50 V / C0G / ±0.1 pF GJM1555C1H2R4BB01 0402 C14 1 Murata
10 Capacitor 0402 / 0.1 µF / 10 V / X7R / ±10% 0402B104K100CT 0402 C3 1 Walsin
11 Capacitor 0402 / 1 µF / 6.3 V / X5R / ±10%/HF GRM155R60J105KE19D 0402 C1 1 Murata
12 Capacitor 0603 / 10 µF / 6.3 V / X5R / ±20% C1608X5R0J106M 0603 C2 1 TDK
13 Resistor 0402 / 0R / ±5% WR04X000 PTL 0402 R1, R3 2 Walsin
For more information, see the Pulse Electronics W3006 product page.

Design Recommendations

This section describes the layout recommendations for the WL1837 module, RF trace, and antenna.

Table 7-2 summarizes the layout recommendations.

Table 7-2 Layout Recommendations Summary

1 The proximity of ground vias must be close to the pad.
2 Signal traces must not be run underneath the module on the layer where the module is mounted.
3 Have a complete ground pour in layer 2 for thermal dissipation.
4 Have a solid ground plane and ground vias under the module for stable system and thermal dissipation.
5 Increase the ground pour in the first layer and have all of the traces from the first layer on the inner layers, if possible.
6 Signal traces can be run on a third layer under the solid ground layer, which is below the module mounting layer.
RF Trace and Antenna Routing
7 The RF trace antenna feed must be as short as possible beyond the ground reference. At this point, the trace starts to radiate.
8 The RF trace bends must be gradual with an approximate maximum bend of 45° with trace mitered. RF traces must not have sharp corners.
9 RF traces must have via stitching on the ground plane beside the RF trace on both sides.
10 RF traces must have constant impedance (microstrip transmission line).
11 For best results, the RF trace ground layer must be the ground layer immediately below the RF trace. The ground layer must be solid.
12 There must be no traces or ground under the antenna section.
13 RF traces must be as short as possible. The antenna, RF traces, and modules must be on the edge of the PCB product. The proximity of the antenna to the enclosure and the enclosure material must also be considered.
Supply and Interface
14 The power trace for VBAT must be at least 40-mil wide.
15 The 1.8-V trace must be at least 18-mil wide.
16 Make VBAT traces as wide as possible to ensure reduced inductance and trace resistance.
17 If possible, shield VBAT traces with ground above, below, and beside the traces.
18 SDIO signals traces (CLK, CMD, D0, D1, D2, and D3) must be routed in parallel to each other and as short as possible (less than 12 cm). In addition, every trace length must be the same as the others. There should be enough space between traces – greater than 1.5 times the trace width or ground – to ensure signal quality, especially for the SDIO_CLK trace. Remember to keep these traces away from the other digital or analog signal traces. TI recommends adding ground shielding around these buses.
19 SDIO and digital clock signals are a source of noise. Keep the traces of these signals as short as possible. If possible, maintain a clearance around them.

RF Trace and Antenna Layout Recommendations

Figure 7-2 shows the location of the antenna on the WL1837MODCOM8I board as well as the RF trace routing from the WL1837 module (TI reference design). The Pulse multilayer antennas are mounted on the board with a specific layout and matching circuit for the radiation test conducted in FCC, CE, and IC certifications.

WL1807MOD WL1837MOD swrs170_layer1.gif Figure 7-2 Location of Antenna and RF Trace Routing on the WL1837MODCOM8I Board

Follow these RF trace routing recommendations:

  • RF traces must have 50-Ω impedance.
  • RF traces must not have sharp corners.
  • RF traces must have via stitching on the ground plane beside the RF trace on both sides.
  • RF traces must be as short as possible. The antenna, RF traces, and module must be on the edge of the PCB product in consideration of the product enclosure material and proximity.

Module Layout Recommendations

Figure 7-3 and Figure 7-4 show layer 1 and layer 2 of the TI module layout.

WL1807MOD WL1837MOD Layer1.png Figure 7-3 TI Module Layout: Layer 1
WL1807MOD WL1837MOD Layer2_solid_ground.png Figure 7-4 TI Module Layout: Layer 2 (Solid GND)

Follow these module layout recommendations:

  • Ensure a solid ground plane and ground vias under the module for stable system and thermal dissipation.
  • Do not run signal traces underneath the module on a layer where the module is mounted.
  • Signal traces can be run on a third layer under the solid ground layer and beneath the module mounting.
  • Run the host interfaces with ground on the adjacent layer to improve the return path.
  • TI recommends routing the signals as short as possible to the host.

Thermal Board Recommendations

    The TI module uses µvias for layers 1 through 6 with full copper filling, providing heat flow all the way to the module ground pads.

    TI recommends using one big ground pad under the module with vias all the way to connect the pad to all ground layers (see Figure 7-5).

    WL1807MOD WL1837MOD SWRS152-21.gif Figure 7-5 Block of Ground Pads on Bottom Side of Package

Figure 7-6 shows via array patterns, which are applied wherever possible to connect all of the layers to the TI module central or main ground pads.

WL1807MOD WL1837MOD SWRS152-22.gif Figure 7-6 Via Array Patterns

Baking and SMT Recommendations

Baking Recommendations

Follow these baking guidelines for the WiLink 8 module:

  • Follow MSL level 3 to perform the baking process.
  • After the bag is open, devices subjected to reflow solder or other high temperature processes must be mounted within 168 hours of factory conditions (< 30°C/60% RH) or stored at <10% RH.
  • If the Humidity Indicator Card reads >10%, devices require baking before they are mounted.
  • If baking is required, bake devices for 8 hours at 125°C.

SMT Recommendations

Figure 7-7 shows the recommended reflow profile for the WiLink 8 module.

WL1807MOD WL1837MOD SWRS152-027.gif Figure 7-7 Reflow Profile for the WiLink 8 Module

Table 7-3 lists the temperature values for the profile shown in Figure 7-7.

Table 7-3 Temperature Values for Reflow Profile

Preheat D1 to approximately D2: 140 to 200 T1: 80 to approximately 120
Soldering D2: 220 T2: 60 ±10
Peak temperature D3: 250 maximum T3: 10


TI does not recommend the use of conformal coating or similar material on the WiLink 8 module. This coating can lead to localized stress on the WCSP solder connections inside the module and impact the device reliability. Care should be taken during module assembly process to the final PCB to avoid the presence of foreign material inside the module.