Refer to the PDF data sheet for device specific package drawings
Information in the following Applications section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Figure 7-1 shows the TI WL1837MODGI reference design.
Table 7-1 lists the bill materials (BOM).
|1||WL1837 Wi-Fi / Bluetooth module||WL1837MODGI||13.4 × 13.3 × 2.0 mm||U1||1||TI|
|2||XOSC 3225 / 32.768 kHz / 1.8 V / ±50 ppm||7XZ3200005||3.2 × 2.5 × 1.0 mm||OSC1||1||TXC|
|3||ANT / Chip / 2.4 GHz and 5 GHz(1)||W3006||10.0 × 3.2 × 1.5 mm||ANT1, ANT2||2||Pulse|
|4||Mini-RF header receptacle||U.FL-R-SMT-1 (10)||3.0 × 2.6 × 1.25 mm||J5, J6||2||Hirose|
|5||Inductor 0402 / 1.3 nH / ±0.1 nH / SMD||LQP15MN1N3B02||0402||L1||1||Murata|
|6||Inductor 0402 / 1.8 nH / ±0.1 nH / SMD||LQP15MN1N8B02||0402||L3||1||Murata|
|7||Inductor 0402 / 2.2 nH / ±0.1 nH / SMD||LQP15MN2N2B02||0402||L4||1||Murata|
|8||Capacitor 0402 / 1 pF/ 50 V / C0G / ±0.1 pF||GJM1555C1H1R0BB01||0402||C13||1||Murata|
|9||Capacitor 0402 / 2.4 pF / 50 V / C0G / ±0.1 pF||GJM1555C1H2R4BB01||0402||C14||1||Murata|
|10||Capacitor 0402 / 0.1 µF / 10 V / X7R / ±10%||0402B104K100CT||0402||C3||1||Walsin|
|11||Capacitor 0402 / 1 µF / 6.3 V / X5R / ±10%/HF||GRM155R60J105KE19D||0402||C1||1||Murata|
|12||Capacitor 0603 / 10 µF / 6.3 V / X5R / ±20%||C1608X5R0J106M||0603||C2||1||TDK|
|13||Resistor 0402 / 0R / ±5%||WR04X000 PTL||0402||R1, R3||2||Walsin|
This section describes the layout recommendations for the WL1837 module, RF trace, and antenna.
Table 7-2 summarizes the layout recommendations.
|1||The proximity of ground vias must be close to the pad.|
|2||Signal traces must not be run underneath the module on the layer where the module is mounted.|
|3||Have a complete ground pour in layer 2 for thermal dissipation.|
|4||Have a solid ground plane and ground vias under the module for stable system and thermal dissipation.|
|5||Increase the ground pour in the first layer and have all of the traces from the first layer on the inner layers, if possible.|
|6||Signal traces can be run on a third layer under the solid ground layer, which is below the module mounting layer.|
|RF Trace and Antenna Routing|
|7||The RF trace antenna feed must be as short as possible beyond the ground reference. At this point, the trace starts to radiate.|
|8||The RF trace bends must be gradual with an approximate maximum bend of 45° with trace mitered. RF traces must not have sharp corners.|
|9||RF traces must have via stitching on the ground plane beside the RF trace on both sides.|
|10||RF traces must have constant impedance (microstrip transmission line).|
|11||For best results, the RF trace ground layer must be the ground layer immediately below the RF trace. The ground layer must be solid.|
|12||There must be no traces or ground under the antenna section.|
|13||RF traces must be as short as possible. The antenna, RF traces, and modules must be on the edge of the PCB product. The proximity of the antenna to the enclosure and the enclosure material must also be considered.|
|Supply and Interface|
|14||The power trace for VBAT must be at least 40-mil wide.|
|15||The 1.8-V trace must be at least 18-mil wide.|
|16||Make VBAT traces as wide as possible to ensure reduced inductance and trace resistance.|
|17||If possible, shield VBAT traces with ground above, below, and beside the traces.|
|18||SDIO signals traces (CLK, CMD, D0, D1, D2, and D3) must be routed in parallel to each other and as short as possible (less than 12 cm). In addition, every trace length must be the same as the others. There should be enough space between traces – greater than 1.5 times the trace width or ground – to ensure signal quality, especially for the SDIO_CLK trace. Remember to keep these traces away from the other digital or analog signal traces. TI recommends adding ground shielding around these buses.|
|19||SDIO and digital clock signals are a source of noise. Keep the traces of these signals as short as possible. If possible, maintain a clearance around them.|
Figure 7-2 shows the location of the antenna on the WL1837MODCOM8I board as well as the RF trace routing from the WL1837 module (TI reference design). The Pulse multilayer antennas are mounted on the board with a specific layout and matching circuit for the radiation test conducted in FCC, CE, and IC certifications.
Follow these RF trace routing recommendations:
Follow these module layout recommendations:
The TI module uses µvias for layers 1 through 6 with full copper filling, providing heat flow all the way to the module ground pads.
TI recommends using one big ground pad under the module with vias all the way to connect the pad to all ground layers (see Figure 7-5).
Figure 7-6 shows via array patterns, which are applied wherever possible to connect all of the layers to the TI module central or main ground pads.
Follow these baking guidelines for the WiLink 8 module:
Figure 7-7 shows the recommended reflow profile for the WiLink 8 module.
|ITEM||TEMPERATURE (°C)||TIME (s)|
|Preheat||D1 to approximately D2: 140 to 200||T1: 80 to approximately 120|
|Soldering||D2: 220||T2: 60 ±10|
|Peak temperature||D3: 250 maximum||T3: 10|
TI does not recommend the use of conformal coating or similar material on the WiLink 8 module. This coating can lead to localized stress on the WCSP solder connections inside the module and impact the device reliability. Care should be taken during module assembly process to the final PCB to avoid the presence of foreign material inside the module.