5.21.1 Power Management

5.21.1.1 Block Diagram – Internal DC-DCs

The device incorporates three internal DC-DCs (switched-mode power supplies) to provide efficient internal supplies, derived from V_BAT.

Figure 5-1 Internal DC-DCs

5.21.2 Power-Up and Shut-Down States

The correct power-up and shut-down sequences must be followed to avoid damage to the device.

While V_BAT or V_IO or both are deasserted, no signals should be driven to the device. The only exception is the slow clock that is a fail-safe I/O.

While V_BAT, V_IO, and slow clock are fed to the device, but WL_EN is deasserted (low), the device is in SHUTDOWN state. In SHUTDOWN state all functional blocks, internal DC-DCs, clocks, and LDOs are disabled.

To perform the correct power-up sequence, assert (high) WL_EN. The internal DC-DCs, LDOs, and clock start to ramp and stabilize. Stable slow clock, V_IO, and V_BAT are prerequisites to the assertion of one of the enable signals.

To perform the correct shut-down sequence, deassert (low) WL_EN while all the supplies to the device (V_BAT, V_IO, and slow clock) are still stable and available. The supplies to the chip (V_BAT and V_IO) can be deasserted only after both enable signals are deasserted (low).

Figure 5-2 shows the general power scheme for the module, including the power-down sequence.

NOTE: 1. Either VBAT or VIO can come up first.

NOTE: 2. VBAT and VIO supplies and slow clock (SCLK), must be stable prior to EN being asserted and at all times

NOTE: when the EN is active.

NOTE: 3. At least 60 µs is required between two successive device enables. The device is assumed to be in

NOTE: shutdown state during that period, meaning all enables to the device are LOW for that minimum duration.

NOTE: 4. EN must be deasserted at least 10 µs before VBAT or VIO supply can be lowered (order of supply turn off

NOTE: after EN shutdown is immaterial).

NOTE: 5. EXT_32K - Fail safe I/O

Figure 5-2 Power-Up System

5.21.3 Chip Top-level Power-Up Sequence

Figure 5-3 shows the top-level power-up sequence for the chip.

Figure 5-3 Chip Top-Level Power-Up Sequence

5.21.4 WLAN Power-Up Sequence

Figure 5-4 shows the WLAN power-up sequence.

Figure 5-4 WLAN Power-Up Sequence

5.21.5 Bluetooth-Bluetooth low energy Power-Up Sequence

Figure 5-5 shows the Bluetooth-Bluetooth low energy power-up sequence.

Figure 5-5 Bluetooth-Bluetooth low energy Power-Up Sequence

5.21.6 WLAN SDIO Transport Layer

The SDIO is the host interface for WLAN. The interface between the host and the WL18xx module uses an SDIO interface and supports a maximum clock rate of 50 MHz.

The device SDIO also supports the following features of the SDIO V3 specification:

• 4-bit data bus
• Synchronous and asynchronous in-band interrupt
• Default and high-speed (HS, 50 MHz) timing
• Sleep and wake commands

5.21.6.1 SDIO Timing Specifications

Figure 5-6 and Figure 5-7 show the SDIO switching characteristics over recommended operating conditions and with the default rate for input and output.

Figure 5-6 SDIO Default Input Timing

Figure 5-7 SDIO Default Output Timing

Table 5-1 lists the SDIO default timing characteristics.

Table 5-1 SDIO Default Timing Characteristics⁽¹⁾

		MIN	MAX	UNIT
fclock	Clock frequency, CLK(2)	0.0	26.0	MHz
DC	Low, high duty cycle(2)	40.0%	60.0%
tTLH	Rise time, CLK(2)		10.0	ns
tTHL	Fall time, CLK(2)		10.0	ns
tISU	Setup time, input valid before CLK ↑(2)	3.0		ns
tIH	Hold time, input valid after CLK ↑(2)	2.0		ns
tODLY	Delay time, CLK ↓ to output valid(2)	7.0	10.0	ns
Cl	Capacitive load on outputs(2)		15.0	pF

(1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit.

(2) Parameter values reflect maximum clock frequency.

5.21.6.2 SDIO Switching Characteristics – High Rate

Figure 5-8 and Figure 5-9 show the parameters for maximum clock frequency.

Figure 5-8 SDIO HS Input Timing

Figure 5-9 SDIO HS Output Timing

Table 5-2 lists the SDIO high-rate timing characteristics.

Table 5-2 SDIO HS Timing Characteristics

		MIN	MAX	UNIT
fclock	Clock frequency, CLK	0.0	52.0	MHz
DC	Low, high duty cycle	40.0%	60.0%
tTLH	Rise time, CLK		3.0	ns
tTHL	Fall time, CLK		3.0	ns
tISU	Setup time, input valid before CLK ↑	3.0		ns
tIH	Hold time, input valid after CLK ↑	2.0		ns
tODLY	Delay time, CLK ↑ to output valid	7.0	10.0	ns
Cl	Capacitive load on outputs		10.0	pF

5.21.7 HCI UART Shared-Transport Layers for All Functional Blocks (Except WLAN)

The device includes a UART module dedicated to the Bluetooth shared-transport, host controller interface (HCI) transport layer. The HCI transports commands, events, and ACL between the Bluetooth device and its host using HCI data packets ack as a shared transport for all functional blocks except WLAN. Table 5-3 lists the transport mechanism for WLAN and bluetooth audio.

_

The HCI UART supports most baud rates (including all PC rates) for all fast-clock frequencies up to a maximum of 4 Mbps. After power up, the baud rate is set for 115.2 Kbps, regardless of the fast-clock frequency. The baud rate can then be changed using a VS command. The device responds with a Command Complete Event (still at 115.2 Kbps), after which the baud rate change occurs.

HCI hardware includes the following features:

• Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions
• Receiver-transmitter underflow detection
• CTS, RTS hardware flow control
• 4 wire (H4)

Table 5-4 lists the UART default settings.

5.21.7.1 UART 4-Wire Interface – H4

The interface includes four signals:

• TXD
• RXD
• CTS
• RTS

Flow control between the host and the device is byte-wise by hardware.

When the UART RX buffer of the device passes the flow-control threshold, the buffer sets the UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high, the device stops transmitting on the interface. If HCI_CTS is set high in the middle of transmitting a byte, the device finishes transmitting the byte and stops the transmission.

Figure 5-10 shows the UART timing.

Figure 5-10 UART Timing Diagram

Table 5-5 lists the UART timing characteristics.

Table 5-5 UART Timing Characteristics

PARAMETER		CONDITION	MIN	TYP	MAX	UNIT
	Baud rate		37.5		4364	Kbps
	Baud rate accuracy per byte	Receive-transmit	–2.5%		1.5%
	Baud rate accuracy per bit	Receive-transmit	–12.5%		12.5%
t3	CTS low to TX_DATA on		0.0	2.0		µs
t4	CTS high to TX_DATA off	Hardware flow control			1.0	Byte
t6	CTS high pulse width		1.0			Bit
t1	RTS low to RX_DATA on		0.0	2.0		µs
t2	RTS high to RX_DATA off	Interrupt set to 1/4 FIFO			16.0	Bytes

Figure 5-11 shows the UART data frame.

Figure 5-11 UART Data Frame

5.21.8 Bluetooth Codec-PCM (Audio) Timing Specifications

Figure 5-12 shows the Bluetooth codec-PCM (audio) timing diagram.

Figure 5-12 Bluetooth Codec-PCM (Audio) Master Timing Diagram

Table 5-6 lists the Bluetooth codec-PCM master timing characteristics.

Table 5-7 lists the Bluetooth codec-PCM slave timing characteristics.