DLPS074
February 2017
DLPC4422
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Schematic
4
Revision History
5
Pin Configuration and Functions
Pin Configurations and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
System Oscillators Timing Requirements
6.7
Test and Reset Timing Requirements
6.8
JTAG Interface: I/O Boundary Scan Application Timing Requirements
6.9
Port 1 Input Pixel Timing Requirements
6.10
Port 3 Input Pixel Interface (via GPIO) Timing Requirements
6.11
DMD LVDS Interface Timing Requirements
6.12
Synchronous Serial Port (SSP) Interface Timing Requirements
6.13
Programmable Output Clocks Switching Characteristics
6.14
Synchronous Serial Port Interface (SSP) Switching Characteristics
6.15
JTAG Interface: I/O Boundary Scan Application Switching Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
System Reset Operation
7.3.1.1
Power-up Reset Operation
7.3.1.2
System Reset Operation
7.3.2
Spread Spectrum Clock Generator Support
7.3.3
GPIO Interface
7.3.4
Source Input Blanking
7.3.5
Video Graphics Processing Delay
7.3.6
Program Memory Flash/SRAM Interface
7.3.7
Calibration and Debug Support
7.3.8
Board Level Test Support
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Recommended MOSC Crystal Oscillator Configuration
8.2.2
Detailed Design Procedure
9
Power Supply Recommendations
9.1
System Power Regulations
9.2
System Power-Up Sequence
9.3
Power-On Sense (POSENSE) Support
9.4
System Environment and Defaults
9.4.1
DLPC4422 System Power-Up and Reset Default Conditions
9.4.2
1.1-V System Power
9.4.3
1.8-V System Power
9.4.4
3.3-V System Power
9.4.5
Power Good (PWRGOOD) Support
9.4.6
5V Tolerant Support
10
Layout
10.1
Layout Guidelines
10.1.1
PCB Layout Guidelines for Internal ASIC Power
10.1.2
PCB Layout Guidelines for Auto-Lock Performance
10.1.3
DMD Interface Considerations
10.1.4
Layout Example
10.1.5
Thermal Considerations
11
Device and Documentation Support
11.1
Device Support
11.1.1
Video Timing Parameter Definitions
11.1.2
Device Nomenclature
11.1.3
Device Markings
11.1.3.1
Device Marking
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
12.1
Package Option Addendum
12.1.1
Packaging Information
封装选项
机械数据 (封装 | 引脚)
ZPC|516
MPBGAJ0
散热焊盘机械数据 (封装 | 引脚)
订购信息
dlps074_oa
1
Features
Provides Two 30-bit Input Pixel Interfaces or One 60-bit Input Pixel Interface:
YUV, YCrCb, or RGB Data Format
8, 9 or 10 Bits per Color
Pixel Clock Support Up to 175 MHz for 30-bit and 160 MHz for 60-bit
Supports 24-30 Hz and 47-120 Hz Frame Rates
Full Single DLP Controller Support For DMD™s Up to 1920 Pixels Wide
Dual DLP Controller Support For Up to 4K Ultra High Definition (UHD) Resolution Display Using DLP660TE TRP DMD
High-Speed, Low Voltage Differential Signaling (LVDS) DMD Interface
150 MHz ARM946™ Microprocessor
Microprocessor Peripherals
Programmable Pulse-Width Modulation (PWM) and Capture Timers
Three I
2
C Ports, Three UART Ports and Three SSP Ports
One USB 1.1 Slave Port
Image Processing
Multiple Image Processing Algorithms
Frame Rate Conversion
Color Coordinate Adjustment
Programmable Color Space Conversion
Programmable Degamma and Splash
Integrated Support for 3-D Display
On-Screen Display (OSD)
Integrated Clock Generation Circuitry
Operates on a Single 20 MHz Crystal
Integrated Spread Spectrum Clocking
External Memory Support
Parallel Flash for Microprocessor and PWM Sequence
Optional SRAM
516 Pin Plastic Ball Grid Array Package
Supports Lamp, LED, and Laser Hybrid Illumination Systems