SNLS500 July   2016 DS90UB964-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings - JEDEC
    3. 6.3 ESD Ratings - IEC and ISO
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 DC Electrical Characteristics
    7. 6.7 AC Electrical Characteristics
    8. 6.8 Recommended Timing for the Serial Control Bus
    9. 6.9 AC Electrical Characteristics
  7. 7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1  RAW Mode
      2. 8.4.2  MODE Pin
      3. 8.4.3  REFCLK
      4. 8.4.4  Input Jitter Tolerance
      5. 8.4.5  Adaptive Equalizer
      6. 8.4.6  Channel Monitor Loop-Through Output Driver
        1. 8.4.6.1 Code Example for CMLOUT FPD3 RX Port 0:
      7. 8.4.7  GPIO Support
        1. 8.4.7.1 Back Channel GPIO
        2. 8.4.7.2 GPIO Pin Status
        3. 8.4.7.3 Other GPIO Pin Controls
      8. 8.4.8  RAW Mode LV/FV Controls
      9. 8.4.9  CSI-2 Protocol Layer
      10. 8.4.10 CSI-2 Short Packet
      11. 8.4.11 CSI-2 Long Packet
      12. 8.4.12 CSI-2 Data Identifier
      13. 8.4.13 Virtual Channel and Context
      14. 8.4.14 CSI-2 Mode Virtual Channel Mapping
        1. 8.4.14.1 Example 1
        2. 8.4.14.2 Example 2
      15. 8.4.15 CSI-2 Transmitter Frequency
      16. 8.4.16 Video Buffers
      17. 8.4.17 CSI-2 Line Count and Line Length
      18. 8.4.18 FrameSync Operation
        1. 8.4.18.1 External FrameSync Control
        2. 8.4.18.2 Internally Generated FrameSync
          1. 8.4.18.2.1 Code Example for Internally Generated FrameSync
      19. 8.4.19 CSI-2 Forwarding
        1. 8.4.19.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 8.4.19.2 Synchronized Forwarding
        3. 8.4.19.3 Basic Synchronized Forwarding
          1. 8.4.19.3.1 Code Example for Basic Synchronized Forwarding
        4. 8.4.19.4 Line-Interleave Forwarding
          1. 8.4.19.4.1 Code Example for Line-Interleave Forwarding
        5. 8.4.19.5 Line-Concatenated Forwarding
          1. 8.4.19.5.1 Code Example for Line-Concatenate Forwarding
        6. 8.4.19.6 CSI-2 Replicate Mode
        7. 8.4.19.7 CSI Transmitter Output Control
    5. 8.5 Programming
      1. 8.5.1 Serial Control Bus
      2. 8.5.2 Second I2C Port
      3. 8.5.3 Broadcast Write to Remote Devices
        1. 8.5.3.1 Code Example for Broadcast Write
      4. 8.5.4 Interrupt Support
        1. 8.5.4.1 Code Example to Enable Interrupts
        2. 8.5.4.2 FPD-Link III Receive Port Interrupts
        3. 8.5.4.3 Code Example to Readback Interrupts
        4. 8.5.4.4 CSI-2 Transmit Port Interrupts
      5. 8.5.5 Timestamp - Video Skew Detection
      6. 8.5.6 Pattern Generation
        1. 8.5.6.1 Code Example for Pattern Generator
      7. 8.5.7 BIST
        1. 8.5.7.1 BIST Configuration and Status
    6. 8.6 Register Description
    7. 8.7 Register Maps
      1. 8.7.1 Indirect Access Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Power Over Coax
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
    1. 10.1 VDD Power Supply
    2. 10.2 Power-Up Sequencing
    3. 10.3 PDB Pin
    4. 10.4 Ground
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 CSI-2 Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40℃ to +105℃ Ambient Operating Temperature Range
    • Device HBM ESD Classification Level ±4 kV
    • Device CDM ESD Classification Level C6
  • Aggregates Data From up to 4 Cameras Over FPD-Link III Interface
  • Supports 1-Megapixel Sensors With HD 720p/800p/960p Resolution at 30-Hz or 60-Hz Frame Rate
  • Multi-Camera Synchronization
  • MIPI DPHY Version 1.2 / CSI-2 Version 1.3 Compliant
    • 2× CSI-2 Output Ports
    • Supports 1, 2, 3, 4 Data Lanes per CSI-2 port
    • CSI-2 Data Rate Scalable for 400 Mbps / 800 Mbps / 1.5 Gbps / 1.6 Gbps each Data Lane
    • Programmable Data Types
    • Four Virtual Channels
    • ECC and CRC Generation
  • Supports Single-Ended Coaxial or Shielded Twisted-Pair (STP) Cable
  • Adaptive Receive Equalization
  • I2C With Fast-Mode Plus up to 1 Mbps
  • Flexible GPIOs for Camera Sync and Functional Safety
  • Compatible With DS90UB913AQ/913Q/933Q Serializers
  • CRC protection on the internal Data Path
  • ISO 10605 and IEC 61000-4-2 ESD Compliant

2 Applications

  • Automotive ADAS
    • Surround View Systems
    • Camera Monitoring Systems
    • Sensor Fusion
  • Security and Surveillance

3 Description

The DS90UB964-Q1 is a versatile camera hub capable of connecting serialized camera data received from 4 independent video datastreams via an FPD-Link III interface. When coupled with DS90UB913AQ/913Q/933Q serializers, the DS90UB964-Q1 receives data from 1-Megapixel image sensors supporting 720p/800p/960p resolution at 30-Hz or 60-Hz frame rates. Data is received and aggregated into a MIPI CSI-2 compliant output for interconnect to a downstream processor. A second MIPI CSI-2 output port is available to provide additional bandwidth, or offers a second replicated output.

The DS90UB964-Q1 includes 4 FPD-Link III deserializers, each enabling a connection via cost-effective 50-Ω single-ended coaxial or 100-Ω differential STP cables. The receive equalizer automatically adapts to compensate for cable loss characteristics, including degradation over time.

Each of the FPD-Link III interfaces also includes a separate low latency bi-directional control channel that conveys control information from an I2C port and is independent of video blanking period. General purpose I/O signals such as those required for camera synchronization and functional safety features also make use of this bi-directional control channel.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UB964-Q1 VQFN (64) 9.00 mm × 9.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

DS90UB964-Q1 964_block_diagram.gif

4 Revision History

DATE REVISION NOTES
July 2016 * Initial release.