JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
Table 58 lists the memory-mapped registers for the SPI_Register_Map registers. All register offset addresses not listed in Table 58 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0x0 | CONFIG_A | Configuration A (default: 0x30) | Go |
0x2 | DEVICE_CONFIG | Device Configuration (default: 0x00) | Go |
0x3 | CHIP_TYPE | Chip Type (Default: 0x03) | Go |
0x4 | CHIP_ID | Chip Identification | Go |
0xC | VENDOR_ID | Vendor Identification (Default = 0x0451) | Go |
0x10 | USR0 | User SPI Configuration (Default: 0x00) | Go |
0x29 | CLK_CTRL0 | Clock Control 0 (default: 0x00) | Go |
0x2A | CLK_CTRL1 | Clock Control 1 (default: 0x00) | Go |
0x2C | SYSREF_POS | SYSREF Capture Position (Read-Only, Default: undefined) | Go |
0x30 | FS_RANGE_A | FS_RANGE_A (default: 0xA000) | Go |
0x32 | FS_RANGE_B | FS_RANGE_B (default: 0xA000) | Go |
0x38 | BG_BYPASS | Band-Gap Bypass (default: 0x00) | Go |
0x3B | TMSTP_CTRL | TMSTP Control (default: 0x00) | Go |
0x48 | SER_PE | Serializer Pre-Emphasis Control (default: 0x00) | Go |
0x60 | INPUT_MUX | Input Mux Control (default: 0x01) | Go |
0x61 | CAL_EN | Calibration Enable (Default: 0x01) | Go |
0x62 | CAL_CFG0 | Calibration Configuration 0 (Default: 0x01) | Go |
0x68 | CAL_AVG | Calibration Averaging (default: 0x61) | Go |
0x6A | CAL_STATUS | Calibration Status (default: undefined) (read-only) | Go |
0x6B | CAL_PIN_CFG | Calibration Pin Configuration (default: 0x00) | Go |
0x6C | CAL_SOFT_TRIG | Calibration Software Trigger (default: 0x01) | Go |
0x6E | CAL_LP | Low-Power Background Calibration (default: 0x88) | Go |
0x70 | CAL_DATA_EN | Calibration Data Enable (default: 0x00) | Go |
0x71 | CAL_DATA | Calibration Data (default: undefined) | Go |
0x7A | GAIN_TRIM_A | Gain DAC Trim A (default from Fuse ROM) | Go |
0x7B | GAIN_TRIM_B | Gain DAC Trim B (default from Fuse ROM) | Go |
0x7C | BG_TRIM | Band-Gap Trim (default from Fuse ROM) | Go |
0x7E | RTRIM_A | Resistor Trim for VinA (default from Fuse ROM) | Go |
0x7F | RTRIM_B | Resistor Trim for VinB (default from Fuse ROM) | Go |
0x9D | ADC_DITH | ADC Dither Control (default from Fuse ROM) | Go |
0x102 | B0_TIME_0 | Time Adjustment for Bank 0 (0° clock) (default from Fuse ROM) | Go |
0x103 | B0_TIME_90 | Time Adjustment for Bank 0 (-90° clock) (default from Fuse ROM) | Go |
0x112 | B1_TIME_0 | Time Adjustment for Bank 1 (0° clock) (default from Fuse ROM) | Go |
0x113 | B1_TIME_90 | Time Adjustment for Bank 1 (-90° clock) (default from Fuse ROM) | Go |
0x142 | B4_TIME_0 | Time Adjustment for Bank 4 (0° clock) (default from Fuse ROM) | Go |
0x152 | B5_TIME_0 | Time Adjustment for Bank 5 (0° clock) (default from Fuse ROM) | Go |
0x160 | LSB_CTRL | LSB Control Bit Output (default: 0x00) | Go |
0x200 | JESD_EN | JESD204C Subsystem Enable (default: 0x01) | Go |
0x201 | JMODE | JESD204C Mode (default: 0x02) | Go |
0x202 | KM1 | JESD204C K Parameter (default: 0x1F) | Go |
0x203 | JSYNC_N | JESD204C Manual Sync Request (default: 0x01) | Go |
0x204 | JCTRL | JESD204C Control (default: 0x02) | Go |
0x205 | JTEST | JESD204C Test Control (default: 0x00) | Go |
0x206 | DID | JESD204C DID Parameter (default: 0x00) | Go |
0x207 | FCHAR | JESD204C Frame Character (default: 0x00) | Go |
0x208 | JESD_STATUS | JESD204C / System Status Register | Go |
0x209 | PD_CH | JESD204C Channel Power Down (default: 0x00) | Go |
0x20A | JEXTRA_A | JESD204C Extra Lane Enable (Link A) (default: 0x00) | Go |
0x20B | JEXTRA_B | JESD204C Extra Lane Enable (Link B) (default: 0x00) | Go |
0x20F | SHMODE | JESD204C Sync Word Mode (default: 0x00) | Go |
0x210 | DDC_CFG | DDC Configuration (default: 0x00) | Go |
0x211 | OVR_T0 | Over-range Threshold 0 (default: 0xF2) | Go |
0x212 | OVR_T1 | Over-range Threshold 1 (default: 0xAB) | Go |
0x213 | OVR_CFG | Over-range Enable / Hold Off (default: 0x07) | Go |
0x214 | CMODE | DDC NCO Configuration Preset Mode (default: 0x00) | Go |
0x215 | CSEL | DDC NCO Configuration Preset Select (default: 0x00) | Go |
0x216 | DIG_BIND | Digital Channel Binding (default: 0x02) | Go |
0x217 | NCO_RDIV | NCO Reference Divisor (default: 0x0000) | Go |
0x219 | NCO_SYNC | NCO Synchronization (default: 0x02) | Go |
0x220 | FREQA0 | NCO Frequency (Channel A, Preset 0) (default: 0xC0000000) | Go |
0x224 | PHASEA0 | NCO Phase (Channel A, Preset 0) (default: 0x0000) | Go |
0x228 | FREQA1 | NCO Frequency (Channel A, Preset 1) (default: 0xC0000000) | Go |
0x22C | PHASEA1 | NCO Phase (Channel A, Preset 1) (default: 0x0000) | Go |
0x230 | FREQA2 | NCO Frequency (Channel A, Preset 2) (default: 0xC0000000) | Go |
0x234 | PHASEA2 | NCO Phase (Channel A, Preset 2) (default: 0x0000) | Go |
0x238 | FREQA3 | NCO Frequency (Channel A, Preset 3) (default: 0xC0000000) | Go |
0x23C | PHASEA3 | NCO Phase (Channel A, Preset 3) (default: 0x0000) | Go |
0x240 | FREQB0 | NCO Frequency (Channel B, Preset 0) (default: 0xC0000000) | Go |
0x244 | PHASEB0 | NCO Phase (Channel B, Preset 0) (default: 0x0000) | Go |
0x248 | FREQB1 | NCO Frequency (Channel B, Preset 1) (default: 0xC0000000) | Go |
0x24C | PHASEB1 | NCO Phase (Channel B, Preset 1) (default: 0x0000) | Go |
0x250 | FREQB2 | NCO Frequency (Channel B, Preset 2) (default: 0xC0000000) | Go |
0x254 | PHASEB2 | NCO Phase (Channel B, Preset 2) (default: 0x0000) | Go |
0x258 | FREQB3 | NCO Frequency (Channel B, Preset 3) (default: 0xC0000000) | Go |
0x25C | PHASEB3 | NCO Phase (Channel B, Preset 3) (default: 0x0000) | Go |
0x297 | SPIN_ID | Chip Spin Identifier (default: See description, read-only) | Go |
0x2B0 | SRC_EN | SYSREF Calibration Enable (default: 0x00) | Go |
0x2B1 | SRC_CFG | SYSREF Calibration Configuration (default: 0x05) | Go |
0x2B2 | SRC_STATUS | SYSREF Calibration Status (read-only, default: undefined) | Go |
0x2B5 | TAD | DEVCLK Timing Adjust (default: 0x00) | Go |
0x2B8 | TAD_RAMP | DEVCLK Timing Adjust Ramp Control (default: 0x00) | Go |
0x2C0 | ALARM | Alarm Interrupt (read-only) | Go |
0x2C1 | ALM_STATUS | Alarm Status (default: 0x3F, write to clear) | Go |
0x2C2 | ALM_MASK | Alarm Mask Register (default: 0x3F) | Go |
0x2C4 | FIFO_LANE_ALM | FIFO Overflow/Underflow Alarm (default: 0xFFFF) | Go |
0x310 | TADJ_A | Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM) | Go |
0x313 | TADJ_B | Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM) | Go |
0x314 | TADJ_A_FG90_VINA | Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM) | Go |
0x315 | TADJ_B_FG0_VINA | Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM) | Go |
0x31A | TADJ_A_FG90_VINB | Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM) | Go |
0x31B | TADJ_B_FG0_VINB | Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM) | Go |
0x344 | OADJ_A_FG0_VINA | Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA± (default from Fuse ROM) | Go |
0x346 | OADJ_A_FG0_VINB | Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB± (default from Fuse ROM) | Go |
0x348 | OADJ_A_FG90_VINA | Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA± (default from Fuse ROM) | Go |
0x34A | OADJ_A_FG90_VINB | Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB± (default from Fuse ROM) | Go |
0x34C | OADJ_B_FG0_VINA | Offset Adjustment for B-ADC sampling INA± (default from Fuse ROM) | Go |
0x34E | OADJ_B_FG0_VINB | Offset Adjustment for B-ADC sampling INB± (default from Fuse ROM) | Go |
0x360 | GAIN_B0 | Fine Gain Adjust for Bank 0 (default from Fuse ROM) | Go |
0x361 | GAIN_B1 | Fine Gain Adjust for Bank 1 (default from Fuse ROM) | Go |
0x364 | GAIN_B4 | Fine Gain Adjust for Bank 4 (default from Fuse ROM) | Go |
0x365 | GAIN_B5 | Fine Gain Adjust for Bank 5 (default from Fuse ROM) | Go |
Complex bit access types are encoded to fit into small table cells. Table 59 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |