JAJSEY1 April   2019 ADC12DJ5200RF

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ADC12DJ5200RF ブロック図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 7.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 7.9  Timing Requirements
    10. 7.10 Switching Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Comparison
      2. 8.3.2 Analog Inputs
        1. 8.3.2.1 Analog Input Protection
        2. 8.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 8.3.2.3 Analog Input Offset Adjust
      3. 8.3.3 ADC Core
        1. 8.3.3.1 ADC Theory of Operation
        2. 8.3.3.2 ADC Core Calibration
        3. 8.3.3.3 Analog Reference Voltage
        4. 8.3.3.4 ADC Overrange Detection
        5. 8.3.3.5 Code Error Rate (CER)
      4. 8.3.4 Temperature Monitoring Diode
      5. 8.3.5 Timestamp
      6. 8.3.6 Clocking
        1. 8.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 8.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 8.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 8.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 8.3.6.3.2 Automatic SYSREF Calibration
      7. 8.3.7 Digital Down Converters (DDC)
        1. 8.3.7.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 8.3.7.1.1 NCO Fast Frequency Hopping (FFH)
          2. 8.3.7.1.2 NCO Selection
          3. 8.3.7.1.3 Basic NCO Frequency Setting Mode
          4. 8.3.7.1.4 Rational NCO Frequency Setting Mode
          5. 8.3.7.1.5 NCO Phase Offset Setting
          6. 8.3.7.1.6 NCO Phase Synchronization
        2. 8.3.7.2 Decimation Filters
        3. 8.3.7.3 Output Data Format
        4. 8.3.7.4 Decimation Settings
          1. 8.3.7.4.1 Decimation Factor
          2. 8.3.7.4.2 DDC Gain Boost
      8. 8.3.8 JESD204C Interface
        1. 8.3.8.1 Transport Layer
        2. 8.3.8.2 Scrambler
        3. 8.3.8.3 Link Layer
        4. 8.3.8.4 8B/10B Link Layer
          1. 8.3.8.4.1 Data Encoding (8B/10B)
          2. 8.3.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 8.3.8.4.3 Code Group Synchronization (CGS)
          4. 8.3.8.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 8.3.8.4.5 Frame and Multiframe Monitoring
        5. 8.3.8.5 64B/66B Link Layer
          1. 8.3.8.5.1 64B/66B Encoding
          2. 8.3.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 8.3.8.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 8.3.8.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 8.3.8.5.3.2 Forward Error Correction (FEC) Mode
          4. 8.3.8.5.4 Initial Lane Alignment
          5. 8.3.8.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 8.3.8.6 Physical Layer
          1. 8.3.8.6.1 SerDes Pre-Emphasis
        7. 8.3.8.7 JESD204C Enable
        8. 8.3.8.8 Multi-Device Synchronization and Deterministic Latency
        9. 8.3.8.9 Operation in Subclass 0 Systems
      9. 8.3.9 Alarm Monitoring
        1. 8.3.9.1 NCO Upset Detection
        2. 8.3.9.2 Clock Upset Detection
        3. 8.3.9.3 FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Dual-Channel Mode
      2. 8.4.2 Single-Channel Mode (DES Mode)
      3. 8.4.3 JESD204C Modes
        1. 8.4.3.1 JESD204C Transport Layer Data Formats
        2. 8.4.3.2 64B/66B Sync Header Stream Configuration
        3. 8.4.3.3 Dual DDC and Redundant Data Mode
      4. 8.4.4 Power-Down Modes
      5. 8.4.5 Test Modes
        1. 8.4.5.1 Serializer Test-Mode Details
        2. 8.4.5.2 PRBS Test Modes
        3. 8.4.5.3 Clock Pattern Mode
        4. 8.4.5.4 Ramp Test Mode
        5. 8.4.5.5 Short and Long Transport Test Mode
          1. 8.4.5.5.1 Short Transport Test Pattern
          2. 8.4.5.5.2 Long Transport Test Pattern
        6. 8.4.5.6 D21.5 Test Mode
        7. 8.4.5.7 K28.5 Test Mode
        8. 8.4.5.8 Repeated ILA Test Mode
        9. 8.4.5.9 Modified RPAT Test Mode
      6. 8.4.6 Calibration Modes and Trimming
        1. 8.4.6.1 Foreground Calibration Mode
        2. 8.4.6.2 Background Calibration Mode
        3. 8.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 8.4.7 Offset Calibration
      8. 8.4.8 Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
        1. 8.5.1.1 SCS
        2. 8.5.1.2 SCLK
        3. 8.5.1.3 SDI
        4. 8.5.1.4 SDO
        5. 8.5.1.5 Streaming Mode
    6. 8.6 SPI_Register_Map Registers
      1. 8.6.1   CONFIG_A Register (Address = 0x0) [reset = 0x30]
        1. Table 60. CONFIG_A Register Field Descriptions
      2. 8.6.2   DEVICE_CONFIG Register (Address = 0x2) [reset = 0x00]
        1. Table 61. DEVICE_CONFIG Register Field Descriptions
      3. 8.6.3   CHIP_TYPE Register (Address = 0x3) [reset = 0x03]
        1. Table 62. CHIP_TYPE Register Field Descriptions
      4. 8.6.4   CHIP_ID Register (Address = 0x4) [reset = 0x0]
        1. Table 63. CHIP_ID Register Field Descriptions
      5. 8.6.5   VENDOR_ID Register (Address = 0xC) [reset = 0x0]
        1. Table 64. VENDOR_ID Register Field Descriptions
      6. 8.6.6   USR0 Register (Address = 0x10) [reset = 0x00]
        1. Table 65. USR0 Register Field Descriptions
      7. 8.6.7   CLK_CTRL0 Register (Address = 0x29) [reset = 0x00]
        1. Table 66. CLK_CTRL0 Register Field Descriptions
      8. 8.6.8   CLK_CTRL1 Register (Address = 0x2A) [reset = 0x00]
        1. Table 67. CLK_CTRL1 Register Field Descriptions
      9. 8.6.9   SYSREF_POS Register (Address = 0x2C) [reset = 0x0]
        1. Table 68. SYSREF_POS Register Field Descriptions
      10. 8.6.10  FS_RANGE_A Register (Address = 0x30) [reset = 0x0]
        1. Table 69. FS_RANGE_A Register Field Descriptions
      11. 8.6.11  FS_RANGE_B Register (Address = 0x32) [reset = 0x0]
        1. Table 70. FS_RANGE_B Register Field Descriptions
      12. 8.6.12  BG_BYPASS Register (Address = 0x38) [reset = 0x00]
        1. Table 71. BG_BYPASS Register Field Descriptions
      13. 8.6.13  TMSTP_CTRL Register (Address = 0x3B) [reset = 0x00]
        1. Table 72. TMSTP_CTRL Register Field Descriptions
      14. 8.6.14  SER_PE Register (Address = 0x48) [reset = 0x00]
        1. Table 73. SER_PE Register Field Descriptions
      15. 8.6.15  INPUT_MUX Register (Address = 0x60) [reset = 0x01]
        1. Table 74. INPUT_MUX Register Field Descriptions
      16. 8.6.16  CAL_EN Register (Address = 0x61) [reset = 0x01]
        1. Table 75. CAL_EN Register Field Descriptions
      17. 8.6.17  CAL_CFG0 Register (Address = 0x62) [reset = 0x01]
        1. Table 76. CAL_CFG0 Register Field Descriptions
      18. 8.6.18  CAL_AVG Register (Address = 0x68) [reset = 0x61]
        1. Table 77. CAL_AVG Register Field Descriptions
      19. 8.6.19  CAL_STATUS Register (Address = 0x6A) [reset = 0x0]
        1. Table 78. CAL_STATUS Register Field Descriptions
      20. 8.6.20  CAL_PIN_CFG Register (Address = 0x6B) [reset = 0x00]
        1. Table 79. CAL_PIN_CFG Register Field Descriptions
      21. 8.6.21  CAL_SOFT_TRIG Register (Address = 0x6C) [reset = 0x01]
        1. Table 80. CAL_SOFT_TRIG Register Field Descriptions
      22. 8.6.22  CAL_LP Register (Address = 0x6E) [reset = 0x88]
        1. Table 81. CAL_LP Register Field Descriptions
      23. 8.6.23  CAL_DATA_EN Register (Address = 0x70) [reset = 0x00]
        1. Table 82. CAL_DATA_EN Register Field Descriptions
      24. 8.6.24  CAL_DATA Register (Address = 0x71) [reset = 0x0]
        1. Table 83. CAL_DATA Register Field Descriptions
      25. 8.6.25  GAIN_TRIM_A Register (Address = 0x7A) [reset = 0x0]
        1. Table 84. GAIN_TRIM_A Register Field Descriptions
      26. 8.6.26  GAIN_TRIM_B Register (Address = 0x7B) [reset = 0x0]
        1. Table 85. GAIN_TRIM_B Register Field Descriptions
      27. 8.6.27  BG_TRIM Register (Address = 0x7C) [reset = 0x0]
        1. Table 86. BG_TRIM Register Field Descriptions
      28. 8.6.28  RTRIM_A Register (Address = 0x7E) [reset = 0x0]
        1. Table 87. RTRIM_A Register Field Descriptions
      29. 8.6.29  RTRIM_B Register (Address = 0x7F) [reset = 0x0]
        1. Table 88. RTRIM_B Register Field Descriptions
      30. 8.6.30  ADC_DITH Register (Address = 0x9D) [reset = 0x0]
        1. Table 89. ADC_DITH Register Field Descriptions
      31. 8.6.31  B0_TIME_0 Register (Address = 0x102) [reset = 0x0]
        1. Table 90. B0_TIME_0 Register Field Descriptions
      32. 8.6.32  B0_TIME_90 Register (Address = 0x103) [reset = 0x0]
        1. Table 91. B0_TIME_90 Register Field Descriptions
      33. 8.6.33  B1_TIME_0 Register (Address = 0x112) [reset = 0x0]
        1. Table 92. B1_TIME_0 Register Field Descriptions
      34. 8.6.34  B1_TIME_90 Register (Address = 0x113) [reset = 0x0]
        1. Table 93. B1_TIME_90 Register Field Descriptions
      35. 8.6.35  B4_TIME_0 Register (Address = 0x142) [reset = 0x0]
        1. Table 94. B4_TIME_0 Register Field Descriptions
      36. 8.6.36  B5_TIME_0 Register (Address = 0x152) [reset = 0x0]
        1. Table 95. B5_TIME_0 Register Field Descriptions
      37. 8.6.37  LSB_CTRL Register (Address = 0x160) [reset = 0x00]
        1. Table 96. LSB_CTRL Register Field Descriptions
      38. 8.6.38  JESD_EN Register (Address = 0x200) [reset = 0x01]
        1. Table 97. JESD_EN Register Field Descriptions
      39. 8.6.39  JMODE Register (Address = 0x201) [reset = 0x02]
        1. Table 98. JMODE Register Field Descriptions
      40. 8.6.40  KM1 Register (Address = 0x202) [reset = 0x1]
        1. Table 99. KM1 Register Field Descriptions
      41. 8.6.41  JSYNC_N Register (Address = 0x203) [reset = 0x01]
        1. Table 100. JSYNC_N Register Field Descriptions
      42. 8.6.42  JCTRL Register (Address = 0x204) [reset = 0x02]
        1. Table 101. JCTRL Register Field Descriptions
      43. 8.6.43  JTEST Register (Address = 0x205) [reset = 0x00]
        1. Table 102. JTEST Register Field Descriptions
      44. 8.6.44  DID Register (Address = 0x206) [reset = 0x00]
        1. Table 103. DID Register Field Descriptions
      45. 8.6.45  FCHAR Register (Address = 0x207) [reset = 0x00]
        1. Table 104. FCHAR Register Field Descriptions
      46. 8.6.46  JESD_STATUS Register (Address = 0x208) [reset = 0x0]
        1. Table 105. JESD_STATUS Register Field Descriptions
      47. 8.6.47  PD_CH Register (Address = 0x209) [reset = 0x00]
        1. Table 106. PD_CH Register Field Descriptions
      48. 8.6.48  JEXTRA_A Register (Address = 0x20A) [reset = 0x00]
        1. Table 107. JEXTRA_A Register Field Descriptions
      49. 8.6.49  JEXTRA_B Register (Address = 0x20B) [reset = 0x00]
        1. Table 108. JEXTRA_B Register Field Descriptions
      50. 8.6.50  SHMODE Register (Address = 0x20F) [reset = 0x00]
        1. Table 109. SHMODE Register Field Descriptions
      51. 8.6.51  DDC_CFG Register (Address = 0x210) [reset = 0x00]
        1. Table 110. DDC_CFG Register Field Descriptions
      52. 8.6.52  OVR_T0 Register (Address = 0x211) [reset = 0x0]
        1. Table 111. OVR_T0 Register Field Descriptions
      53. 8.6.53  OVR_T1 Register (Address = 0x212) [reset = 0x0]
        1. Table 112. OVR_T1 Register Field Descriptions
      54. 8.6.54  OVR_CFG Register (Address = 0x213) [reset = 0x07]
        1. Table 113. OVR_CFG Register Field Descriptions
      55. 8.6.55  CMODE Register (Address = 0x214) [reset = 0x00]
        1. Table 114. CMODE Register Field Descriptions
      56. 8.6.56  CSEL Register (Address = 0x215) [reset = 0x00]
        1. Table 115. CSEL Register Field Descriptions
      57. 8.6.57  DIG_BIND Register (Address = 0x216) [reset = 0x02]
        1. Table 116. DIG_BIND Register Field Descriptions
      58. 8.6.58  NCO_RDIV Register (Address = 0x217) [reset = 0x0000]
        1. Table 117. NCO_RDIV Register Field Descriptions
      59. 8.6.59  NCO_SYNC Register (Address = 0x219) [reset = 0x02]
        1. Table 118. NCO_SYNC Register Field Descriptions
      60. 8.6.60  FREQA0 Register (Address = 0x220) [reset = 0x0]
        1. Table 119. FREQA0 Register Field Descriptions
      61. 8.6.61  PHASEA0 Register (Address = 0x224) [reset = 0x0000]
        1. Table 120. PHASEA0 Register Field Descriptions
      62. 8.6.62  FREQA1 Register (Address = 0x228) [reset = 0x0]
        1. Table 121. FREQA1 Register Field Descriptions
      63. 8.6.63  PHASEA1 Register (Address = 0x22C) [reset = 0x0000]
        1. Table 122. PHASEA1 Register Field Descriptions
      64. 8.6.64  FREQA2 Register (Address = 0x230) [reset = 0x0]
        1. Table 123. FREQA2 Register Field Descriptions
      65. 8.6.65  PHASEA2 Register (Address = 0x234) [reset = 0x0000]
        1. Table 124. PHASEA2 Register Field Descriptions
      66. 8.6.66  FREQA3 Register (Address = 0x238) [reset = 0x0]
        1. Table 125. FREQA3 Register Field Descriptions
      67. 8.6.67  PHASEA3 Register (Address = 0x23C) [reset = 0x0000]
        1. Table 126. PHASEA3 Register Field Descriptions
      68. 8.6.68  FREQB0 Register (Address = 0x240) [reset = 0x0]
        1. Table 127. FREQB0 Register Field Descriptions
      69. 8.6.69  PHASEB0 Register (Address = 0x244) [reset = 0x0000]
        1. Table 128. PHASEB0 Register Field Descriptions
      70. 8.6.70  FREQB1 Register (Address = 0x248) [reset = 0x0]
        1. Table 129. FREQB1 Register Field Descriptions
      71. 8.6.71  PHASEB1 Register (Address = 0x24C) [reset = 0x0000]
        1. Table 130. PHASEB1 Register Field Descriptions
      72. 8.6.72  FREQB2 Register (Address = 0x250) [reset = 0x0]
        1. Table 131. FREQB2 Register Field Descriptions
      73. 8.6.73  PHASEB2 Register (Address = 0x254) [reset = 0x0000]
        1. Table 132. PHASEB2 Register Field Descriptions
      74. 8.6.74  FREQB3 Register (Address = 0x258) [reset = 0x0]
        1. Table 133. FREQB3 Register Field Descriptions
      75. 8.6.75  PHASEB3 Register (Address = 0x25C) [reset = 0x0000]
        1. Table 134. PHASEB3 Register Field Descriptions
      76. 8.6.76  SPIN_ID Register (Address = 0x297) [reset = 0x0]
        1. Table 135. SPIN_ID Register Field Descriptions
      77. 8.6.77  SRC_EN Register (Address = 0x2B0) [reset = 0x00]
        1. Table 136. SRC_EN Register Field Descriptions
      78. 8.6.78  SRC_CFG Register (Address = 0x2B1) [reset = 0x05]
        1. Table 137. SRC_CFG Register Field Descriptions
      79. 8.6.79  SRC_STATUS Register (Address = 0x2B2) [reset = 0x0]
        1. Table 138. SRC_STATUS Register Field Descriptions
      80. 8.6.80  TAD Register (Address = 0x2B5) [reset = 0x00]
        1. Table 139. TAD Register Field Descriptions
      81. 8.6.81  TAD_RAMP Register (Address = 0x2B8) [reset = 0x00]
        1. Table 140. TAD_RAMP Register Field Descriptions
      82. 8.6.82  ALARM Register (Address = 0x2C0) [reset = 0x0]
        1. Table 141. ALARM Register Field Descriptions
      83. 8.6.83  ALM_STATUS Register (Address = 0x2C1) [reset = 0x3]
        1. Table 142. ALM_STATUS Register Field Descriptions
      84. 8.6.84  ALM_MASK Register (Address = 0x2C2) [reset = 0x3]
        1. Table 143. ALM_MASK Register Field Descriptions
      85. 8.6.85  FIFO_LANE_ALM Register (Address = 0x2C4) [reset = 0x0]
        1. Table 144. FIFO_LANE_ALM Register Field Descriptions
      86. 8.6.86  TADJ_A Register (Address = 0x310) [reset = 0x0]
        1. Table 145. TADJ_A Register Field Descriptions
      87. 8.6.87  TADJ_B Register (Address = 0x313) [reset = 0x0]
        1. Table 146. TADJ_B Register Field Descriptions
      88. 8.6.88  TADJ_A_FG90_VINA Register (Address = 0x314) [reset = 0x0]
        1. Table 147. TADJ_A_FG90_VINA Register Field Descriptions
      89. 8.6.89  TADJ_B_FG0_VINA Register (Address = 0x315) [reset = 0x0]
        1. Table 148. TADJ_B_FG0_VINA Register Field Descriptions
      90. 8.6.90  TADJ_A_FG90_VINB Register (Address = 0x31A) [reset = 0x0]
        1. Table 149. TADJ_A_FG90_VINB Register Field Descriptions
      91. 8.6.91  TADJ_B_FG0_VINB Register (Address = 0x31B) [reset = 0x0]
        1. Table 150. TADJ_B_FG0_VINB Register Field Descriptions
      92. 8.6.92  OADJ_A_FG0_VINA Register (Address = 0x344) [reset = 0x0]
        1. Table 151. OADJ_A_FG0_VINA Register Field Descriptions
      93. 8.6.93  OADJ_A_FG0_VINB Register (Address = 0x346) [reset = 0x0]
        1. Table 152. OADJ_A_FG0_VINB Register Field Descriptions
      94. 8.6.94  OADJ_A_FG90_VINA Register (Address = 0x348) [reset = 0x0]
        1. Table 153. OADJ_A_FG90_VINA Register Field Descriptions
      95. 8.6.95  OADJ_A_FG90_VINB Register (Address = 0x34A) [reset = 0x0]
        1. Table 154. OADJ_A_FG90_VINB Register Field Descriptions
      96. 8.6.96  OADJ_B_FG0_VINA Register (Address = 0x34C) [reset = 0x0]
        1. Table 155. OADJ_B_FG0_VINA Register Field Descriptions
      97. 8.6.97  OADJ_B_FG0_VINB Register (Address = 0x34E) [reset = 0x0]
        1. Table 156. OADJ_B_FG0_VINB Register Field Descriptions
      98. 8.6.98  GAIN_B0 Register (Address = 0x360) [reset = 0x0]
        1. Table 157. GAIN_B0 Register Field Descriptions
      99. 8.6.99  GAIN_B1 Register (Address = 0x361) [reset = 0x0]
        1. Table 158. GAIN_B1 Register Field Descriptions
      100. 8.6.100 GAIN_B4 Register (Address = 0x364) [reset = 0x0]
        1. Table 159. GAIN_B4 Register Field Descriptions
      101. 8.6.101 GAIN_B5 Register (Address = 0x365) [reset = 0x0]
        1. Table 160. GAIN_B5 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Wideband RF Sampling Receiver
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 Input Signal Path
          2. 9.2.1.1.2 Clocking
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Calculating Values of AC-Coupling Capacitors
      2. 9.2.2 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Input Signal Path
          2. 9.2.2.1.2 Clocking
          3. 9.2.2.1.3 ADC12DJ5200RF
    3. 9.3 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6 SPI_Register_Map Registers

Table 58 lists the memory-mapped registers for the SPI_Register_Map registers. All register offset addresses not listed in Table 58 should be considered as reserved locations and the register contents should not be modified.

Table 58. SPI_REGISTER_MAP Registers

Offset Acronym Register Name Section
0x0 CONFIG_A Configuration A (default: 0x30) Go
0x2 DEVICE_CONFIG Device Configuration (default: 0x00) Go
0x3 CHIP_TYPE Chip Type (Default: 0x03) Go
0x4 CHIP_ID Chip Identification Go
0xC VENDOR_ID Vendor Identification (Default = 0x0451) Go
0x10 USR0 User SPI Configuration (Default: 0x00) Go
0x29 CLK_CTRL0 Clock Control 0 (default: 0x00) Go
0x2A CLK_CTRL1 Clock Control 1 (default: 0x00) Go
0x2C SYSREF_POS SYSREF Capture Position (Read-Only, Default: undefined) Go
0x30 FS_RANGE_A FS_RANGE_A (default: 0xA000) Go
0x32 FS_RANGE_B FS_RANGE_B (default: 0xA000) Go
0x38 BG_BYPASS Band-Gap Bypass (default: 0x00) Go
0x3B TMSTP_CTRL TMSTP Control (default: 0x00) Go
0x48 SER_PE Serializer Pre-Emphasis Control (default: 0x00) Go
0x60 INPUT_MUX Input Mux Control (default: 0x01) Go
0x61 CAL_EN Calibration Enable (Default: 0x01) Go
0x62 CAL_CFG0 Calibration Configuration 0 (Default: 0x01) Go
0x68 CAL_AVG Calibration Averaging (default: 0x61) Go
0x6A CAL_STATUS Calibration Status (default: undefined) (read-only) Go
0x6B CAL_PIN_CFG Calibration Pin Configuration (default: 0x00) Go
0x6C CAL_SOFT_TRIG Calibration Software Trigger (default: 0x01) Go
0x6E CAL_LP Low-Power Background Calibration (default: 0x88) Go
0x70 CAL_DATA_EN Calibration Data Enable (default: 0x00) Go
0x71 CAL_DATA Calibration Data (default: undefined) Go
0x7A GAIN_TRIM_A Gain DAC Trim A (default from Fuse ROM) Go
0x7B GAIN_TRIM_B Gain DAC Trim B (default from Fuse ROM) Go
0x7C BG_TRIM Band-Gap Trim (default from Fuse ROM) Go
0x7E RTRIM_A Resistor Trim for VinA (default from Fuse ROM) Go
0x7F RTRIM_B Resistor Trim for VinB (default from Fuse ROM) Go
0x9D ADC_DITH ADC Dither Control (default from Fuse ROM) Go
0x102 B0_TIME_0 Time Adjustment for Bank 0 (0° clock) (default from Fuse ROM) Go
0x103 B0_TIME_90 Time Adjustment for Bank 0 (-90° clock) (default from Fuse ROM) Go
0x112 B1_TIME_0 Time Adjustment for Bank 1 (0° clock) (default from Fuse ROM) Go
0x113 B1_TIME_90 Time Adjustment for Bank 1 (-90° clock) (default from Fuse ROM) Go
0x142 B4_TIME_0 Time Adjustment for Bank 4 (0° clock) (default from Fuse ROM) Go
0x152 B5_TIME_0 Time Adjustment for Bank 5 (0° clock) (default from Fuse ROM) Go
0x160 LSB_CTRL LSB Control Bit Output (default: 0x00) Go
0x200 JESD_EN JESD204C Subsystem Enable (default: 0x01) Go
0x201 JMODE JESD204C Mode (default: 0x02) Go
0x202 KM1 JESD204C K Parameter (default: 0x1F) Go
0x203 JSYNC_N JESD204C Manual Sync Request (default: 0x01) Go
0x204 JCTRL JESD204C Control (default: 0x02) Go
0x205 JTEST JESD204C Test Control (default: 0x00) Go
0x206 DID JESD204C DID Parameter (default: 0x00) Go
0x207 FCHAR JESD204C Frame Character (default: 0x00) Go
0x208 JESD_STATUS JESD204C / System Status Register Go
0x209 PD_CH JESD204C Channel Power Down (default: 0x00) Go
0x20A JEXTRA_A JESD204C Extra Lane Enable (Link A) (default: 0x00) Go
0x20B JEXTRA_B JESD204C Extra Lane Enable (Link B) (default: 0x00) Go
0x20F SHMODE JESD204C Sync Word Mode (default: 0x00) Go
0x210 DDC_CFG DDC Configuration (default: 0x00) Go
0x211 OVR_T0 Over-range Threshold 0 (default: 0xF2) Go
0x212 OVR_T1 Over-range Threshold 1 (default: 0xAB) Go
0x213 OVR_CFG Over-range Enable / Hold Off (default: 0x07) Go
0x214 CMODE DDC NCO Configuration Preset Mode (default: 0x00) Go
0x215 CSEL DDC NCO Configuration Preset Select (default: 0x00) Go
0x216 DIG_BIND Digital Channel Binding (default: 0x02) Go
0x217 NCO_RDIV NCO Reference Divisor (default: 0x0000) Go
0x219 NCO_SYNC NCO Synchronization (default: 0x02) Go
0x220 FREQA0 NCO Frequency (Channel A, Preset 0) (default: 0xC0000000) Go
0x224 PHASEA0 NCO Phase (Channel A, Preset 0) (default: 0x0000) Go
0x228 FREQA1 NCO Frequency (Channel A, Preset 1) (default: 0xC0000000) Go
0x22C PHASEA1 NCO Phase (Channel A, Preset 1) (default: 0x0000) Go
0x230 FREQA2 NCO Frequency (Channel A, Preset 2) (default: 0xC0000000) Go
0x234 PHASEA2 NCO Phase (Channel A, Preset 2) (default: 0x0000) Go
0x238 FREQA3 NCO Frequency (Channel A, Preset 3) (default: 0xC0000000) Go
0x23C PHASEA3 NCO Phase (Channel A, Preset 3) (default: 0x0000) Go
0x240 FREQB0 NCO Frequency (Channel B, Preset 0) (default: 0xC0000000) Go
0x244 PHASEB0 NCO Phase (Channel B, Preset 0) (default: 0x0000) Go
0x248 FREQB1 NCO Frequency (Channel B, Preset 1) (default: 0xC0000000) Go
0x24C PHASEB1 NCO Phase (Channel B, Preset 1) (default: 0x0000) Go
0x250 FREQB2 NCO Frequency (Channel B, Preset 2) (default: 0xC0000000) Go
0x254 PHASEB2 NCO Phase (Channel B, Preset 2) (default: 0x0000) Go
0x258 FREQB3 NCO Frequency (Channel B, Preset 3) (default: 0xC0000000) Go
0x25C PHASEB3 NCO Phase (Channel B, Preset 3) (default: 0x0000) Go
0x297 SPIN_ID Chip Spin Identifier (default: See description, read-only) Go
0x2B0 SRC_EN SYSREF Calibration Enable (default: 0x00) Go
0x2B1 SRC_CFG SYSREF Calibration Configuration (default: 0x05) Go
0x2B2 SRC_STATUS SYSREF Calibration Status (read-only, default: undefined) Go
0x2B5 TAD DEVCLK Timing Adjust (default: 0x00) Go
0x2B8 TAD_RAMP DEVCLK Timing Adjust Ramp Control (default: 0x00) Go
0x2C0 ALARM Alarm Interrupt (read-only) Go
0x2C1 ALM_STATUS Alarm Status (default: 0x3F, write to clear) Go
0x2C2 ALM_MASK Alarm Mask Register (default: 0x3F) Go
0x2C4 FIFO_LANE_ALM FIFO Overflow/Underflow Alarm (default: 0xFFFF) Go
0x310 TADJ_A Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM) Go
0x313 TADJ_B Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM) Go
0x314 TADJ_A_FG90_VINA Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM) Go
0x315 TADJ_B_FG0_VINA Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM) Go
0x31A TADJ_A_FG90_VINB Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM) Go
0x31B TADJ_B_FG0_VINB Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM) Go
0x344 OADJ_A_FG0_VINA Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA± (default from Fuse ROM) Go
0x346 OADJ_A_FG0_VINB Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB± (default from Fuse ROM) Go
0x348 OADJ_A_FG90_VINA Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA± (default from Fuse ROM) Go
0x34A OADJ_A_FG90_VINB Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB± (default from Fuse ROM) Go
0x34C OADJ_B_FG0_VINA Offset Adjustment for B-ADC sampling INA± (default from Fuse ROM) Go
0x34E OADJ_B_FG0_VINB Offset Adjustment for B-ADC sampling INB± (default from Fuse ROM) Go
0x360 GAIN_B0 Fine Gain Adjust for Bank 0 (default from Fuse ROM) Go
0x361 GAIN_B1 Fine Gain Adjust for Bank 1 (default from Fuse ROM) Go
0x364 GAIN_B4 Fine Gain Adjust for Bank 4 (default from Fuse ROM) Go
0x365 GAIN_B5 Fine Gain Adjust for Bank 5 (default from Fuse ROM) Go

Complex bit access types are encoded to fit into small table cells. Table 59 shows the codes that are used for access types in this section.

Table 59. SPI_Register_Map Access Type Codes

Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value
Register Array Variables
i,j,k,l,m,n When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y When this variable is used in a register name, an offset, or an address it refers to the value of a register array.