8.6.8 CLK_CTRL1 Register (Address = 0x2A) [reset = 0x00]
CLK_CTRL1 is shown in Figure 31 and described in Table 67.
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Clock Control 1 (default: 0x00)
Figure 31. CLK_CTRL1 Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
SYSREF_TIME_STAMP_EN |
DEVCLK_LVPECL_EN |
SYSREF_LVPECL_EN |
SYSREF_INVERTED |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 67. CLK_CTRL1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7:4 |
RESERVED |
R/W |
0x0 |
|
3 |
SYSREF_TIME_STAMP_EN |
R/W |
0x0 |
The SYSREF signal can be observed on the LSB of the JESD204C output samples when SYSREF_TIMESTAMP_EN and TIME_STAMP_EN are both set. Only supported in DDC bypass modes (i.e. D=1). This bit allows SYSREF± to be used as the timestamp input.
|
2 |
DEVCLK_LVPECL_EN |
R/W |
0x0 |
Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin Functions table.
|
1 |
SYSREF_LVPECL_EN |
R/W |
0x0 |
Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the Pin Functions table.
|
0 |
SYSREF_INVERTED |
R/W |
0x0 |
This bit inverts the SYSREF signal used for alignment.
|