8.6.22 CAL_LP Register (Address = 0x6E) [reset = 0x88]
CAL_LP is shown in Figure 45 and described in Table 81.
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Low-Power Background Calibration (default: 0x88)
Figure 45. CAL_LP Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
LP_SLEEP_DLY |
LP_WAKE_DLY |
RESERVED |
LP_TRIG |
LP_EN |
R/W-0x4 |
R/W-0x1 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 81. CAL_LP Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7:5 |
LP_SLEEP_DLY |
R/W |
0x4 |
These bits adjust how long an ADC sleeps before waking for calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values below 4 are not recommended because of limited overall power reduction benefits.
0: Sleep delay = (23 + 1) × 256 × tCLK
1: Sleep delay = (215 + 1) × 256 × tCLK
2: Sleep delay = (218 + 1) × 256 × tCLK
3: Sleep delay = (221 + 1) × 256 × tCLK
4: Sleep delay = (224 + 1) × 256 × tCLK (default, approximately 1.338 seconds with a 3.2-GHz clock)
5: Sleep delay = (227 + 1) × 256 × tCLK
6: Sleep delay = (230 + 1) × 256 × tCLK
7: Sleep delay = (233 + 1) × 256 × tCLK
|
4:3 |
LP_WAKE_DLY |
R/W |
0x1 |
These bits adjust how much time is provided for settling before calibrating an ADC after the ADC wakes up (only applies when LP_EN = 1). Values lower than 1 are not recommended because there is insufficient time for the core to stabilize before calibration begins.
0: Wake delay = (23 + 1) × 256 × tCLK
1: Wake delay = (218 + 1) × 256 × tCLK (default, approximately 21 ms with a 3.2-GHz clock)
2: Wake delay = (221 + 1) × 256 × tCLK
3: Wake delay = (224 + 1) × 256 × tCLK
|
2 |
RESERVED |
R/W |
0x0 |
|
1 |
LP_TRIG |
R/W |
0x0 |
0 : ADC sleep duration is set by LP_SLEEP_DLY (autonomous mode).
1 : ADCs sleep until awoken by a trigger. An ADC is awoken when the calibration trigger is low.
|
0 |
LP_EN |
R/W |
0x0 |
0 : Disable low-power background calibration (default)
1 : Enable low-power background calibration (only applies when CAL_BG=1).
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