8.6.51 DDC_CFG Register (Address = 0x210) [reset = 0x00]
DDC_CFG is shown in Figure 74 and described in Table 110.
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DDC Configuration (default: 0x00)
Figure 74. DDC_CFG Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
BOOST |
R/W-0x0 |
R/W-0x0 |
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Table 110. DDC_CFG Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7:1 |
RESERVED |
R/W |
0x0 |
|
0 |
BOOST |
R/W |
0x0 |
DDC gain control.
0 : DDC filter has 0dB gain (default).
1 : DDC filter has 6.02dB gain. Only use this setting when you are certain the negative image of your input signal is filtered out by the DDC, otherwise clipping may occur.
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