| 7:6 |
RESERVED |
R/W |
0x0 |
|
| 5 |
FIFO_ALM |
R/W |
0x0 |
FIFO overflow/underflow alarm: This bit is set whenever an active JESD204C lane FIFO experiences an underflow or overflow condition. Write a ‘1’ to clear this bit. To inspect which lane generated the alarm, read FIFO_LANE_ALM.
|
| 4 |
PLL_ALM |
R/W |
0x0 |
PLL Lock Lost Alarm: This bit is set whenever the PLL is not locked. Write a ‘1’ to clear this bit.
|
| 3 |
LINK_ALM |
R/W |
0x0 |
Link Alarm: This bit is set whenever the JESD204C link is enabled, but is not in the data encoder state (for 8B/10B modes). In 64B/66B modes, there is no data encoder state, so this alarm will be set when the link first starts up, and will also be set if any event causes a FIFO/serializer realignment. Write a ‘1’ to clear this bit.
|
| 2 |
REALIGNED_ALM |
R/W |
0x0 |
Realigned Alarm: This bit is set whenever SYSREF causes the internal clocks (including the LMFC/LEMC) to be realigned. Write a ‘1’ to clear this bit.
|
| 1 |
NCO_ALM |
R/W |
0x1 |
NCO Alarm: This bit can be used to detect an upset to the NCO phase. This bit is set when any of the following occur:
- The NCOs are disabled (JESD_EN=0).
- The NCOs are synchronized (intentionally or unintentionally)
- Any phase accumulators in channel A do not match channel B.
Write a ‘1’ to clear this bit. Refer to the alarm section for the proper usage of this register.
|
| 0 |
CLK_ALM |
R/W |
0x1 |
Clock Alarm: This bit can be used to detect an upset to the internal DDC/JESD204C clocks. This bit is set whenever the internal clock dividers for the A and B channels do not match. Write a ‘1’ to clear this bit. Refer to the alarm section for the proper usage of this register.
Note: After power-on reset or soft-reset, all alarm bits are set to ‘1.’
Note: When JESD_EN=0, all alarms (except CLK_ALM) are undefined. It is recommended that the user clears the alarms after setting JESD_EN=1.
|