8.6.85 FIFO_LANE_ALM Register (Address = 0x2C4) [reset = 0x0]
FIFO_LANE_ALM is shown in Figure 108 and described in Table 144.
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FIFO Overflow/Underflow Alarm (default: 0xFFFF)
Figure 108. FIFO_LANE_ALM Register
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
FIFO_LANE_ALM |
R/W-0x0 |
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Table 144. FIFO_LANE_ALM Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15:0 |
FIFO_LANE_ALM |
R/W |
0x0 |
FIFO_LANE_ALM[i] is set if the FIFO for lane i experiences overflow or underflow. Use this register to determine which lane(s) generated an alarm. Writing a ‘1’ to any bit in this register will clear the alarm (the alarm may immediately trip again if the overflow/underflow condition persists). Writing a ‘1’ to the FIFO_ALM bit in the ALM_STATUS register will clear all bits of this register.
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