JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
The input offset voltage for each input and for each ADC core can be adjusted through SPI registers. The OADJ_A_FG0_VINx and OADJ_A_FG90_VINx registers (registers 0x344 to 0x34A) are used to adjust ADC core A's offset voltage when sampling analog input x (where x is A for INA± or B for INB±) where the FG0 register is used for dual channel mode and FG90 is used for single channel mode. OADJ_B_FG0_VINx is used to adjust ADC core B's offset voltage when sampling input x. OADJ_B_FG0_VINx applies to both single channel mode and dual channel mode. To adjust the offset voltage in dual channel mode simply adjust the offset for the ADC core sampling the desired input. In single channel mode, both ADC core A's offset and ADC core B's offset must be adjusted together. The difference in the two core's offsets in single channel mode will result in a spur at fS/2 that is independent of the input. These registers can be used to compensate the fS/2 spur in single channel mode. See the Calibration Modes and Trimming section for more information.