JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
The ADC12DJ5200RF uses a JESD204C high-speed serial interface for data converters to transfer data from the ADC to the receiving logic device. Many of the available JESD204C output formats are backwards compatible with existing JESD204B receivers, including many of the JESD204B modes in the ADC12DJ2700 and ADC12DJ3200. The ADC12DJ5200RF serialized lanes are capable of operating with both 8B/10B encoding and 64B/66B encoding. A maximum of 16 lanes can be used to lower lane rates for interfacing with speed-limited logic devices. There are a few differences between 8B/10B and 64B/66B encoded JESD204C, which will be described throughout this section. Figure 14 shows a simplified block diagram of the 8B/10B encoded JESD204C interface and Figure 15 shows a simplified block diagram of the 64B/66B encoded JESD204C interface.
The various signals used in the JESD204C interface and the associated ADC12DJ5200RF pin names are summarized briefly in Table 15 for reference. Most of the signals are common between 8B/10B and 64B/66B encoded JESD204C, except for SYNC which is not needed to achieve block synchronization for 64B/66B encoding. The sync header encoded into the data stream is used for block synchronization instead of the SYNC signal.
|SIGNAL NAME||ADC12DJ5200RF PIN NAMES||8B/10B||64B/66B||DESCRIPTION|
|Data||DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)||Yes||Yes||High-speed serialized data after 8B/10B or 64B/66B encoding|
|SYNC||SYNCSE, TMSTP+, TMSTP–||Yes||No||Link initialization signal (handshake), toggles low to start code group synchronization (CGS) process. Not used for 64B/66B encoding modes, unless it is used for NCO synchronization purposes.|
|Device clock||CLK+, CLK–||Yes||Yes||ADC sampling clock, also used for clocking digital logic and output serializers|
|SYSREF||SYSREF+, SYSREF–||Yes||Yes||System timing reference used to deterministically reset the internal local multiframe clock (LMFC) or local extended multiblock clock (LEMC) counters in each JESD204C device|
Not all optional features of JESD204C are supported by ADC12DJ5200RF. The list of features that are supported and the features that are not supported is provided in Table 16.
|LETTER IDENTIFIER||REFERENCE CLAUSE||FEATURE||SUPPORT IN ADC12DJ5200RF|
|a||clause 8||8B/10B link layer||Supported|
|b||clause 7||64B/66B link layer||Supported|
|c||clause 7||64B/80B link layer||Not supported|
|d||clause 7||The command channel when using the 64B/66B or 64B/80B link layer||Not supported|
|e||clause 7||Forward error correction (FEC) when using the 64B/66B or 64B/80B link layer||Supported|
|f||clause 7||CRC3 when using the 64B/66B or 64B/80B link layer||Not supported|
|g||clause 8||A physical SYNC pin when using the 8B/10B link layer||Supported|
|h||clause 7, clause 8||Subclass 0||Not supported, but subclass 1 transmitter is compatible with subclass 0 receiver|
|i||clause 7, clause 8||Subclass 1||Supported|
|j||clause 8||Subclass 2||Not supported|
|k||clause 7, clause 8||Lane alignment within a single link||Supported|
|l||clause 7, clause 8||Subclass 1 with support for a lane alignment on a multipoint link by means of the MULTIREF signal||Not supported|
|m||clause 8||SYNC interface timing is compatible with JESD204A||Supported|
|n||clause 8||SYNC interface timing is compatible with JESD204B||Supported|