JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
ADC12DJ5200RF can operate with subclass 0 compatibility provided that multi-ADC synchronization and deterministic latency are not required. With these limitations, the device can operate without the application of SYSREF. The internal LMFC/LEMC is automatically self-generated with unknown timing. SYNC is used as normal to initiate the CGS and ILAS in 8B/10B mode.