JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
The NCO_ALM register bit indicates if the NCO in channel A or B has been upset. The NCO phase accumulators in channel A are continuously compared to channel B. If the accumulators differ for even one clock cycle, the NCO_ALM register bit is set and remains set until cleared by the host system by writing a 1. This feature requires the phase and frequency words for each NCO accumulator in DDC A (PHASEAx, FREQAx) to be set to the same values as the NCO accumulators in DDC B (PHASEBx, FREQBx). For example, PHASEA0 must be the same as PHASEB0 and FREQA0 must be the same as FREQB0, however, PHASEA1 can be set to a different value than PHASEA0. This requirement ultimately reduces the number of NCO frequencies available for phase coherent frequency hopping from four to two for each DDC. DDC B can use a different NCO frequency than DDC A by setting the NCOB[1:0] pins to a different value than NCOA[1:0]. This detection is only valid after the NCOs are synchronized by either SYSREF or the start of the ILA sequence (as determined by the NCO synchronization register). For the NCO upset detection to work properly, follow these steps: