JAJSEY1D April   2019  – July 2022 ADC12DJ5200RF

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Comparison
      2. 7.3.2  Analog Inputs
        1. 7.3.2.1 Analog Input Protection
        2. 7.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.2.3 Analog Input Offset Adjust
      3. 7.3.3  ADC Core
        1. 7.3.3.1 ADC Theory of Operation
        2. 7.3.3.2 ADC Core Calibration
        3. 7.3.3.3 Analog Reference Voltage
        4. 7.3.3.4 ADC Overrange Detection
        5. 7.3.3.5 Code Error Rate (CER)
      4. 7.3.4  Temperature Monitoring Diode
      5. 7.3.5  Timestamp
      6. 7.3.6  Clocking
        1. 7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.6.3.2 Automatic SYSREF Calibration
      7. 7.3.7  Programmable FIR Filter (PFIR)
        1. 7.3.7.1 Dual Channel Equalization
        2. 7.3.7.2 Single Channel Equalization
        3. 7.3.7.3 Time Varying Filter
      8. 7.3.8  Digital Down Converters (DDC)
        1. 7.3.8.1 Rounding and Saturation
        2. 7.3.8.2 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.8.2.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.8.2.2 NCO Selection
          3. 7.3.8.2.3 Basic NCO Frequency Setting Mode
          4. 7.3.8.2.4 Rational NCO Frequency Setting Mode
          5. 7.3.8.2.5 NCO Phase Offset Setting
          6. 7.3.8.2.6 NCO Phase Synchronization
        3. 7.3.8.3 Decimation Filters
        4. 7.3.8.4 Output Data Format
        5. 7.3.8.5 Decimation Settings
          1. 7.3.8.5.1 Decimation Factor
          2. 7.3.8.5.2 DDC Gain Boost
      9. 7.3.9  JESD204C Interface
        1. 7.3.9.1 Transport Layer
        2. 7.3.9.2 Scrambler
        3. 7.3.9.3 Link Layer
        4. 7.3.9.4 8B/10B Link Layer
          1. 7.3.9.4.1 Data Encoding (8B/10B)
          2. 7.3.9.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.9.4.3 Code Group Synchronization (CGS)
          4. 7.3.9.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.9.4.5 Frame and Multiframe Monitoring
        5. 7.3.9.5 64B/66B Link Layer
          1. 7.3.9.5.1 64B/66B Encoding
          2. 7.3.9.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.9.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.9.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.9.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.9.5.4 Initial Lane Alignment
          5. 7.3.9.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.9.6 Physical Layer
          1. 7.3.9.6.1 SerDes Pre-Emphasis
        7. 7.3.9.7 JESD204C Enable
        8. 7.3.9.8 Multi-Device Synchronization and Deterministic Latency
        9. 7.3.9.9 Operation in Subclass 0 Systems
      10. 7.3.10 Alarm Monitoring
        1. 7.3.10.1 Clock Upset Detection
        2. 7.3.10.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Operating Modes Table
        2. 7.4.4.2 JESD204C Modes continued
        3. 7.4.4.3 JESD204C Transport Layer Data Formats
        4. 7.4.4.4 64B/66B Sync Header Stream Configuration
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI Register Map
  8. Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 ADC12DJ5200RF
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
  9. Power Supply Recommendations
    1. 9.1 Power Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 145
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

SPI Register Map

Table 7-36 lists the SPI_Register_Map registers. All register offset addresses not listed in Table 7-36 should be considered as reserved locations and the register contents should not be modified.

Table 7-36 SPI REGISTER MAP Registers
AddressAcronymRegister NameSection
0x0CONFIG_AConfiguration A (default: 0x30)Go
0x2DEVICE_CONFIGDevice Configuration (default: 0x00)Go
0x3CHIP_TYPEChip Type (Default: 0x03)Go
0x4CHIP_IDChip IdentificationGo
0xCVENDOR_IDVendor Identification (Default = 0x0451)Go
0x10USR0User SPI Configuration (Default: 0x00)Go
0x29CLK_CTRL0Clock Control 0 (default: 0x00)Go
0x2ACLK_CTRL1Clock Control 1 (default: 0x00)Go
0x02BCLK_CNTL2Clock Control 2 (default: 0x11)Go
0x2CSYSREF_POSSYSREF Capture Position (Read-Only, Default: undefined)Go
0x30FS_RANGE_AFS_RANGE_A (default: 0xA000)Go
0x32FS_RANGE_BFS_RANGE_B (default: 0xA000)Go
0x38BG_BYPASSBand-Gap Bypass (default: 0x00)Go
0x3BTMSTP_CTRLTMSTP Control (default: 0x00)Go
0x48SER_PESerializer Pre-Emphasis Control (default: 0x00)Go
0x60INPUT_MUXInput Mux Control (default: 0x01)Go
0x61CAL_ENCalibration Enable (Default: 0x01)Go
0x62CAL_CFG0Calibration Configuration 0 (Default: 0x01)Go
0x64CAL_CFG2Calibration Configuration 0 (Default: 0x02)Go
0x68CAL_AVGCalibration Averaging (default: 0x61)Go
0x6ACAL_STATUSCalibration Status (default: undefined) (read-only)Go
0x6BCAL_PIN_CFGCalibration Pin Configuration (default: 0x00)Go
0x6CCAL_SOFT_TRIGCalibration Software Trigger (default: 0x01)Go
0x6ECAL_LPLow-Power Background Calibration (default: 0x88)Go
0x70CAL_DATA_ENCalibration Data Enable (default: 0x00)Go
0x71CAL_DATACalibration Data (default: undefined)Go
0x7AGAIN_TRIM_AGain DAC Trim A (default from Fuse ROM)Go
0x7BGAIN_TRIM_BGain DAC Trim B (default from Fuse ROM)Go
0x7CBG_TRIMBand-Gap Trim (default from Fuse ROM)Go
0x7ERTRIM_AResistor Trim for VinA (default from Fuse ROM)Go
0x7FRTRIM_BResistor Trim for VinB (default from Fuse ROM)Go
0x9DADC_DITHADC Dither Control (default from Fuse ROM)Go
0x160LSB_CTRLLSB Control Bit Output (default: 0x00)Go
0x200JESD_ENJESD204C Subsystem Enable (default: 0x01)Go
0x201JMODEJESD204C Mode (default: 0x02)Go
0x202KM1JESD204C K Parameter (default: 0x1F)Go
0x203JSYNC_NJESD204C Manual Sync Request (default: 0x01)Go
0x204JCTRLJESD204C Control (default: 0x03)Go
0x205JTESTJESD204C Test Control (default: 0x00)Go
0x206DIDJESD204C DID Parameter (default: 0x00)Go
0x207FCHARJESD204C Frame Character (default: 0x00)Go
0x208JESD_STATUSJESD204C / System Status RegisterGo
0x209PD_CHJESD204C Channel Power Down (default: 0x00)Go
0x20AJEXTRA_AJESD204C Extra Lane Enable (Link A) (default: 0x00)Go
0x20BJEXTRA_BJESD204C Extra Lane Enable (Link B) (default: 0x00)Go
0x20FSHMODEJESD204C Sync Word Mode (default: 0x00)Go
0x210DDC_CFGDDC Configuration (default: 0x00)Go
0x211OVR_T0Over-range Threshold 0 (default: 0xF2)Go
0x212OVR_T1Over-range Threshold 1 (default: 0xAB)Go
0x213OVR_CFGOver-range Enable / Hold Off (default: 0x07)Go
0x214CMODEDDC NCO Configuration Preset Mode (default: 0x00)Go
0x215CSELDDC NCO Configuration Preset Select (default: 0x00)Go
0x216DIG_BINDDigital Channel Binding (default: 0x02)Go
0x217NCO_RDIVNCO Reference Divisor (default: 0x0000)Go
0x219NCO_SYNCNCO Synchronization (default: 0x02)Go
0x220FREQA0NCO Frequency (Channel A, Preset 0) (default: 0xC0000000)Go
0x224PHASEA0NCO Phase (Channel A, Preset 0) (default: 0x0000)Go
0x228FREQA1NCO Frequency (Channel A, Preset 1) (default: 0xC0000000)Go
0x22CPHASEA1NCO Phase (Channel A, Preset 1) (default: 0x0000)Go
0x230FREQA2NCO Frequency (Channel A, Preset 2) (default: 0xC0000000)Go
0x234PHASEA2NCO Phase (Channel A, Preset 2) (default: 0x0000)Go
0x238FREQA3NCO Frequency (Channel A, Preset 3) (default: 0xC0000000)Go
0x23CPHASEA3NCO Phase (Channel A, Preset 3) (default: 0x0000)Go
0x240FREQB0NCO Frequency (Channel B, Preset 0) (default: 0xC0000000)Go
0x244PHASEB0NCO Phase (Channel B, Preset 0) (default: 0x0000)Go
0x248FREQB1NCO Frequency (Channel B, Preset 1) (default: 0xC0000000)Go
0x24CPHASEB1NCO Phase (Channel B, Preset 1) (default: 0x0000)Go
0x250FREQB2NCO Frequency (Channel B, Preset 2) (default: 0xC0000000)Go
0x254PHASEB2NCO Phase (Channel B, Preset 2) (default: 0x0000)Go
0x258FREQB3NCO Frequency (Channel B, Preset 3) (default: 0xC0000000)Go
0x25CPHASEB3NCO Phase (Channel B, Preset 3) (default: 0x0000)Go
0x270INIT_STATUSInitialization Status (read-only)Go
0x297SPIN_IDChip Spin Identifier (default: See description, read-only)Go
0x2A2TESTBUSAnalog Test Bus Control (default: 0x00)Go
0x2B0SRC_ENSYSREF Calibration Enable (default: 0x00)Go
0x2B1SRC_CFGSYSREF Calibration Configuration (default: 0x05)Go
0x2B2SRC_STATUSSYSREF Calibration Status (read-only, default: undefined)Go
0x2B5TADDEVCLK Timing Adjust (default: 0x00)Go
0x2B8TAD_RAMPDEVCLK Timing Adjust Ramp Control (default: 0x00)Go
0x2C0ALARMAlarm Interrupt (read-only)Go
0x2C1ALM_STATUSAlarm Status (default: 0x3F, write to clear)Go
0x2C2ALM_MASKAlarm Mask Register (default: 0x3F)Go
0x2C4FIFO_LANE_ALMFIFO Overflow/Underflow Alarm (default: 0xFFFF)Go
0x310TADJ_ATiming Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM)Go
0x313TADJ_BTiming Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM)Go
0x314TADJ_A_FG90_VINATiming Adjust for A-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM)Go
0x315TADJ_B_FG0_VINATiming Adjust for B-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM)Go
0x31ATADJ_A_FG90_VINBTiming Adjust for A-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM)Go
0x31BTADJ_B_FG0_VINBTiming Adjust for B-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM)Go
0x344OADJ_A_FG0_VINAOffset Adjustment for A-ADC operating in Dual Channel Mode sampling INA± (default from Fuse ROM)Go
0x346OADJ_A_FG0_VINBOffset Adjustment for A-ADC operating in Dual Channel Mode sampling INB± (default from Fuse ROM)Go
0x348OADJ_A_FG90_VINAOffset Adjustment for A-ADC operating in Single Channel Mode sampling INA± (default from Fuse ROM)Go
0x34AOADJ_A_FG90_VINBOffset Adjustment for A-ADC operating in Single Channel Mode sampling INB± (default from Fuse ROM)Go
0x34COADJ_B_FG0_VINAOffset Adjustment for B-ADC sampling INA± (default from Fuse ROM)Go
0x34EOADJ_B_FG0_VINBOffset Adjustment for B-ADC sampling INB± (default from Fuse ROM)Go
0x350GAIN_A0_FGDUALFine Gain Adjust for ADC A Bank 0 in Dual Channel Mode (default from Fuse ROM)Go
0x351GAIN_A1_FGDUALFine Gain Adjust for ADC A Bank 1 in Dual Channel Mode (default from Fuse ROM)Go
0x352GAIN_B0_FGDUALFine Gain Adjust for ADC B Bank 0 in Dual Channel Mode (default from Fuse ROM)Go
0x353GAIN_B1_FGDUALFine Gain Adjust for ADC B Bank 1 in Dual Channel Mode (default from Fuse ROM)Go
0x354GAIN_A0_FGDESFine Gain Adjust for ADC A Bank 0 in Single Channel Mode (default from Fuse ROM)Go
0x355GAIN_A1_FGDESFine Gain Adjust for ADC A Bank 1 in Single Channel Mode (default from Fuse ROM)Go
0x356GAIN_B0_FGDESFine Gain Adjust for ADC B Bank 0 in Single Channel Mode (default from Fuse ROM)Go
0x357GAIN_B1_FGDESFine Gain Adjust for ADC B Bank 1 in Single Channel Mode (default from Fuse ROM)Go
0x400PFIR_CFGProgrammable FIR Mode (default: 0x00)Go
0x418PFIR_A0PFIR Coefficient A0Go
0x41APFIR_A1PFIR Coefficient A1Go
0x41CPFIR_A2PFIR Coefficient A2Go
0x41EPFIR_A3PFIR Coefficient A3Go
0x420PFIR_A4PFIR Coefficient A4Go
0x423PFIR_A5PFIR Coefficient A5Go
0x425PFIR_A6PFIR Coefficient A6Go
0x427PFIR_A7PFIR Coefficient A7Go
0x429PFIR_A8PFIR Coefficient A8Go
0x448PFIR_B0PFIR Coefficient B0Go
0x44APFIR_B1PFIR Coefficient B1Go
0x44CPFIR_B2PFIR Coefficient B2Go
0x44EPFIR_B3PFIR Coefficient B3Go
0x450PFIR_B4PFIR Coefficient B4Go
0x453PFIR_B5PFIR Coefficient B5Go
0x455PFIR_B6PFIR Coefficient B6Go
0x457PFIR_B7PFIR Coefficient B7Go
0x459PFIR_B8PFIR Coefficient B8Go

Complex bit access types are encoded to fit into small table cells. Table 7-37 shows the codes that are used for access types in this section.

Table 7-37 SPI_Register_Map Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

7.6.1 CONFIG_A Register (Address = 0x0) [reset = 0x30]

CONFIG_A is shown in Figure 7-28 and described in Table 7-38.

Return to the Summary Table.

Configuration A (default: 0x30)

Figure 7-28 CONFIG_A Register
76543210
SOFT_RESETRESERVEDASCENDSDO_ACTIVERESERVED
R/W-0x0R/W-0x0R/W-0x1R-0x1R/W-0x0
Table 7-38 CONFIG_A Register Field Descriptions
BitFieldTypeResetDescription
7SOFT_RESETR/W0x0

Setting this bit causes a full reset of the chip and all SPI registers (including CONFIG_A). This bit is self-clearing. After writing this bit, the part may take up to 750ns to reset. During this time, do not perform any SPI transactions.

6RESERVEDR/W0x0
5ASCENDR/W0x1

0 : Address is decremented during streaming reads/writes
1 : Address is incremented during streaming reads/writes (default)

4SDO_ACTIVER0x1

Always returns 1. Always use SDO for SPI reads.
No SDIO mode supported.

3:0RESERVEDR/W0x0

7.6.2 DEVICE_CONFIG Register (Address = 0x2) [reset = 0x00]

DEVICE_CONFIG is shown in Figure 7-29 and described in Table 7-39.

Return to the Summary Table.

Device Configuration (default: 0x00)

Figure 7-29 DEVICE_CONFIG Register
76543210
RESERVEDMODE
R/W-0x0R/W-0x0
Table 7-39 DEVICE_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0
1:0MODER/W0x0

0 : Normal operation (default)
1 : Reserved
2 : Reserved
3 : Power down (lowest power, slower resume)

7.6.3 CHIP_TYPE Register (Address = 0x3) [reset = 0x03]

CHIP_TYPE is shown in Figure 7-30 and described in Table 7-40.

Return to the Summary Table.

Chip Type (Default: 0x03)

Figure 7-30 CHIP_TYPE Register
76543210
RESERVEDCHIP_TYPE
R/W-0x0R-0x3
Table 7-40 CHIP_TYPE Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0
3:0CHIP_TYPER0x3

Always returns 0x3, indicating that the part is a high speed ADC.

7.6.4 CHIP_ID Register (Address = 0x4) [reset = 0x0]

CHIP_ID is shown in Figure 7-31 and described in Table 7-41.

Return to the Summary Table.

Chip Identification

Figure 7-31 CHIP_ID Register
15141312111098
CHIP_ID
R-0x0
76543210
CHIP_ID
R-0x0
Table 7-41 CHIP_ID Register Field Descriptions
BitFieldTypeResetDescription
15:0CHIP_IDR0x0

Returns 0x0021 indicating the device is in the ADCrrDJssssRF family.

7.6.5 VENDOR_ID Register (Address = 0xC) [reset = 0x0]

VENDOR_ID is shown in Figure 7-32 and described in Table 7-42.

Return to the Summary Table.

Vendor Identification (Default = 0x0451)

Figure 7-32 VENDOR_ID Register
15141312111098
VENDOR_ID
R-0x0
76543210
VENDOR_ID
R-0x0
Table 7-42 VENDOR_ID Register Field Descriptions
BitFieldTypeResetDescription
15:0VENDOR_IDR0x0

Always returns 0x0451 (Vendor ID for Texas Instruments)

7.6.6 USR0 Register (Address = 0x10) [reset = 0x00]

USR0 is shown in Figure 7-33 and described in Table 7-43.

Return to the Summary Table.

User SPI Configuration (Default: 0x00)

Figure 7-33 USR0 Register
76543210
RESERVEDADDR_HOLD
R/W-0x0R/W-0x0
Table 7-43 USR0 Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0
0ADDR_HOLDR/W0x0

0 : Use ASCEND register to select address ascend/descend mode (default)
1 : Address stays constant throughout streaming operation; useful for reading and writing calibration vector information at the CAL_DATA register

7.6.7 CLK_CTRL0 Register (Address = 0x29) [reset = 0x00]

CLK_CTRL0 is shown in Figure 7-34 and described in Table 7-44.

Return to the Summary Table.

Clock Control 0 (default: 0x00)

Figure 7-34 CLK_CTRL0 Register
76543210
RESERVEDSYSREF_PROC_ENSYSREF_RECV_ENSYSREF_ZOOMSYSREF_SEL
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 7-44 CLK_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0
6SYSREF_PROC_ENR/W0x0

This bit enables the SYSREF processor, which allows the device to process SYSREF events (default: disabled). SYSREF_RECV_EN must be set before setting SYSREF_PROC_EN.

5SYSREF_RECV_ENR/W0x0

Set this bit to enable the SYSREF receiver circuit (default: disabled)

4SYSREF_ZOOMR/W0x0

Set this bit to zoom in the SYSREF windowing status and delays (impacts SYSERF_POS and SYSREF_SEL). When set, the delays used in the SYSREF windowing feature (reported in the SYSREF_POS register) become smaller. Use SYSREF_ZOOM for high clock rates, specifically when multiple SYSREF valid windows are encountered in the SYSREF_POS register; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section.

3:0SYSREF_SELR/W0x0

Set this field to select which SYSREF delay to use. Set this field based on the results returned by SYSREF_POS; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section. These bits must be set to 0 to use SYSREF calibration; see the Automatic SYSREF Calibration section.

7.6.8 CLK_CTRL1 Register (Address = 0x2A) [reset = 0x00]

CLK_CTRL1 is shown in Figure 7-35 and described in Table 7-45.

Return to the Summary Table.

Clock Control 1 (default: 0x00)

Figure 7-35 CLK_CTRL1 Register
76543210
RESERVEDSYSREF_TIME_STAMP_ENDEVCLK_LVPECL_ENSYSREF_LVPECL_ENSYSREF_INVERTED
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 7-45 CLK_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0
3SYSREF_TIME_STAMP_ENR/W0x0

The SYSREF signal can be observed on the LSB of the JESD204C output samples when SYSREF_TIMESTAMP_EN and TIME_STAMP_EN are both set. Only supported in DDC bypass modes (i.e. D=1). This bit allows SYSREF± to be used as the timestamp input.

2DEVCLK_LVPECL_ENR/W0x0

Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin Functions table.

1SYSREF_LVPECL_ENR/W0x0

Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the Pin Functions table.

0SYSREF_INVERTEDR/W0x0

This bit inverts the SYSREF signal used for alignment.

7.6.9 CLK_CTRL2 Register (Address = 0x02B) [reset = 0x11]

CLK_CTRL2 is shown in and described in Figure 7-36 and described in Table 7-46.

Return to the Summary Table.

Clock Control 2 (default: 0x11)

Figure 7-36 CLK_CTRL2 Register
76543210
RESERVEDC_CLK_FEEDBACK_GAINReservedEN_VA11_NOISE_SUPPRCLKSAMP_DEL
R/W-0x0R/W-0x1R/W-0x0R/W-0x0R/W-0x1
Table 7-46 CLK_CTRL2 Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4C_CLK_FEEDBACK_GAINR/W0x1

Adjustable feedback gain for CMLtoCMOS converter (high gain:1)

3ReservedR/W0x0

Reserved

2EN_VA11_NOISE_SUPPRR/W0x0

When set, noise on VA11 is suppressed. It is recommended to have this set, as it reduces noise coupling from the digital circuits to analog clock, at the expense of a small increase in power.

1:0CLKSAMP_DELR/W0x1

Adjustable delay for the sampling clock (one hot encoded)

7.6.10 SYSREF_POS Register (Address = 0x2C) [reset = 0x0]

SYSREF_POS is shown in Figure 7-37 and described in Table 7-47.

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SYSREF Capture Position (Read-Only, Default: undefined)

Figure 7-37 SYSREF_POS Register
2322212019181716
SYSREF_POS
R/W-0x0
15141312111098
SYSREF_POS
R/W-0x0
76543210
SYSREF_POS
R/W-0x0
Table 7-47 SYSREF_POS Register Field Descriptions
BitFieldTypeResetDescription
23:0SYSREF_POSR/W0x0

Returns a 24-bit status value that indicates the position of the SYSREF edge with respect to CLK±. Use this to program SYSREF_SEL.

7.6.11 FS_RANGE_A Register (Address = 0x30) [reset = 0xA000]

FS_RANGE_A is shown in Figure 7-38 and described in Table 7-48.

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FS_RANGE_A (default: 0xA000)

Figure 7-38 FS_RANGE_A Register
15141312111098
FS_RANGE_A
R/W-0xA000
76543210
FS_RANGE_A
R/W-0xA000
Table 7-48 FS_RANGE_A Register Field Descriptions
BitFieldTypeResetDescription
15:0FS_RANGE_AR/W0xA000

These bits enable adjustment of the analog full-scale range for INA±.
0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting

7.6.12 FS_RANGE_B Register (Address = 0x32) [reset = 0xA000]

FS_RANGE_B is shown in Figure 7-39 and described in Table 7-49.

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FS_RANGE_B (default: 0xA000)

Figure 7-39 FS_RANGE_B Register
15141312111098
FS_RANGE_B
R/W-0xA000
76543210
FS_RANGE_B
R/W-0xA000
Table 7-49 FS_RANGE_B Register Field Descriptions
BitFieldTypeResetDescription
15:0FS_RANGE_BR/W0xA000

These bits enable adjustment of the analog full-scale range for INB±.
0x0000: Settings below 0x2000 result in degraded performance
0x2000: 500 mVPP - Recommended minimum setting
0xA000: 800 mVPP (default)
0xFFFF: 1000 mVPP - Maximum setting

7.6.13 BG_BYPASS Register (Address = 0x38) [reset = 0x00]

BG_BYPASS is shown in Figure 7-40 and described in Table 7-50.

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Band-Gap Bypass (default: 0x00)

Figure 7-40 BG_BYPASS Register
76543210
RESERVEDBG_BYPASS
R/W-0x0R/W-0x0
Table 7-50 BG_BYPASS Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0
0BG_BYPASSR/W0x0

When set, VA11 is used as the voltage reference instead of the band-gap voltage.

7.6.14 TMSTP_CTRL Register (Address = 0x3B) [reset = 0x00]

TMSTP_CTRL is shown in Figure 7-41 and described in Table 7-51.

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TMSTP Control (default: 0x00)

Figure 7-41 TMSTP_CTRL Register
76543210
RESERVEDTMSTP_LVPECL_ENTMSTP_RECV_EN
R/W-0x0R/W-0x0R/W-0x0
Table 7-51 TMSTP_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0
1TMSTP_LVPECL_ENR/W0x0

When set, activates the low voltage PECL mode for the differential TMSTP± input.

0TMSTP_RECV_ENR/W0x0

Enables the differential differential TMSTP± input.

7.6.15 SER_PE Register (Address = 0x48) [reset = 0x00]

SER_PE is shown in Figure 7-42 and described in Table 7-52.

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Serializer Pre-Emphasis Control (default: 0x00)

Figure 7-42 SER_PE Register
76543210
RESERVEDSER_PE_BOOSTSER_PE
R/W-0x0R/W-0x0R/W-0x0
Table 7-52 SER_PE Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0
3SER_PE_BOOSTR/W0x0Additional pre-emphesis boost that increases the pre-emphesis slightly and extends it in time.
2:0SER_PER/W0x0

Sets the pre-emphasis for the SerDes output lanes. Pre-emphasis can be used to compensate for the high-frequency loss of the PCB trace. This is a global setting that affects all 16 lanes (DA[7:0]±, DB[7:0]±).

7.6.16 INPUT_MUX Register (Address = 0x60) [reset = 0x01]

INPUT_MUX is shown in Figure 7-43 and described in Table 7-53.

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Input Mux Control (default: 0x01)

Figure 7-43 INPUT_MUX Register
76543210
RESERVEDDUAL_INPUTRESERVEDSINGLE_INPUT
R/W-0x0R/W-0x0R/W-0x0R/W-0x1
Table 7-53 INPUT_MUX Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4DUAL_INPUTR/W0x0

Select inputs for dual channel modes. If JMODE is selecting a single channel mode, this register has no effect.
0: A channel samples INA±, B channel samples INB± (no swap) (default)
1: A channel samples INB±, B channel samples INA± (swap)

3:2RESERVEDR/W0x0
1:0SINGLE_INPUTR/W0x1

Defines which input is sampled in single channel mode. If JMODE is not selecting a single channel mode, this register has no effect.
0: RESERVED
1: INA± is used (default)
2: INB± is used
3: ADC channel A samples INA± and ADC channel B samples INB± (DUAL DES mode). A calibration needs to be performance after switching the input mux for the changes to take effect.

7.6.17 CAL_EN Register (Address = 0x61) [reset = 0x01]

CAL_EN is shown in Figure 7-44 and described in Table 7-54.

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Calibration Enable (Default: 0x01)

Figure 7-44 CAL_EN Register
76543210
RESERVEDCAL_EN
R/W-0x0R/W-0x1
Table 7-54 CAL_EN Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0
0CAL_ENR/W0x1

Calibration Enable. Set high to run calibration. Set low to hold calibration in reset to program new calibration settings. Clearing CAL_EN also resets the clock dividers that clock the digital block and JESD204C interface.

Some calibration registers require clearing CAL_EN before making any changes. All registers with this requirement contain a note in their descriptions. After changing the registers, set CAL_EN to re-run calibration with the new settings. Always set CAL_EN before setting JESD_EN. Always clear JESD_EN before clearing CAL_EN.

7.6.18 CAL_CFG0 Register (Address = 0x62) [reset = 0x01]

CAL_CFG0 is shown in Figure 7-45 and described in Table 7-55.

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Calibration Configuration 0 (Default: 0x01)

Figure 7-45 CAL_CFG0 Register
76543210
RESERVEDCAL_BGOSCAL_OSCAL_BGCAL_FG
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x1
Table 7-55 CAL_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0
3CAL_BGOSR/W0x0

0 : Disable background offset calibration (default)
1 : Enable background offset calibration (requires CAL_BG to be set).

2CAL_OSR/W0x0

0 : Disable foreground offset calibration (default)
1 : Enable foreground offset calibration (requires CAL_FG to be set).

1CAL_BGR/W0x0

0 : Disable background calibration (default)
1 : Enable background calibration

0CAL_FGR/W0x1

0 : Reset calibration values, skip foreground calibration.
1 : Reset calibration values, then run foreground calibration (default).

7.6.19 CAL_CFG2 Register (Address = 0x64) [reset = 0x02]

CAL_CFG2 is shown in Figure 7-46and described in Table 7-56.

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Calibration Configuration 2 (Default: 0x02)

Figure 7-46 CAL_CFG2 Register
76543210
RESERVEDADC_OFF
R/W-0x00R/W-0x10
Table 7-56 CAL_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x00Reserved
1:0ADC_OFFR/W0x1If background calibration is disabled, this selects which ADC will be disabled and never calibrated. Only change ADC_OFF while JESD_EN is 0.

0 : ADC0 (ADC1 will stand in for ADC0)

1 : ADC1

2 : ADC2 (ADC1 will stand in for ADC2)

3 : Reserved

7.6.20 CAL_AVG Register (Address = 0x68) [reset = 0x61]

CAL_AVG is shown in Figure 7-47 and described in Table 7-57.

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Calibration Averaging (default: 0x61)

Figure 7-47 CAL_AVG Register
76543210
RESERVEDOS_AVGRESERVEDCAL_AVG
R/W-0x0R/W-0x6R/W-0x0R/W-0x1
Table 7-57 CAL_AVG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0
6:4OS_AVGR/W0x6

Select the amount of averaging used for the offset correction routine. A larger number corresponds to more averaging.

3RESERVEDR/W0x0
2:0CAL_AVGR/W0x1

Select the amount of averaging used for the linearity calibration routine. A larger number corresponds to more averaging.

7.6.21 CAL_STATUS Register (Address = 0x6A) [reset = 0x0]

CAL_STATUS is shown in Figure 7-48 and described in Table 7-58.

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Calibration Status (default: undefined) (read-only)

Figure 7-48 CAL_STATUS Register
76543210
RESERVEDCAL_STATCAL_STOPPEDFG_DONE
R-0x0R-0x0R-0x0R-0x0
Table 7-58 CAL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0
4:2CAL_STATR0x0

Calibration status code

1CAL_STOPPEDR0x0

This bit returns a 1 when background calibration is successfully stopped at the requested phase. This bit returns a 0 when calibration starts operating again. If background calibration is disabled, this bit is set when foreground calibration is completed or skipped.

0FG_DONER0x0

This bit is high to indicate that foreground calibration has completed (or was skipped).

7.6.22 CAL_PIN_CFG Register (Address = 0x6B) [reset = 0x00]

CAL_PIN_CFG is shown in Figure 7-49 and described in Table 7-59.

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Calibration Pin Configuration (default: 0x00)

Figure 7-49 CAL_PIN_CFG Register
76543210
RESERVEDCAL_STATUS_SELCAL_TRIG_EN
R/W-0x0R/W-0x0R/W-0x0
Table 7-59 CAL_PIN_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR/W0x0
2:1CAL_STATUS_SELR/W0x0

0 : CALSTAT output matches FG_DONE.
1 : CALSTAT output matches CAL_STOPPED.
2 : CALSTAT output matches ALARM.
3 : CALSTAT output is always low.

0CAL_TRIG_ENR/W0x0

This bit selects the hardware or software trigger source.
0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The CALTRIG input is disabled (ignored).
1 : Use the CALTRIG input for the calibration trigger. The CAL_SOFT_TRIG register is ignored.

7.6.23 CAL_SOFT_TRIG Register (Address = 0x6C) [reset = 0x01]

CAL_SOFT_TRIG is shown in Figure 7-50 and described in Table 7-60.

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Calibration Software Trigger (default: 0x01)

Figure 7-50 CAL_SOFT_TRIG Register
76543210
RESERVEDCAL_SOFT_TRIG
R/W-0x0R/W-0x1
Table 7-60 CAL_SOFT_TRIG Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0
0CAL_SOFT_TRIGR/W0x1

CAL_SOFT_TRIG is a software bit to provide the functionality of the CALTRIG input pin when there are no hardware resources to drive CALTRIG. Program CAL_TRIG_EN=0 to use CAL_SOFT_TRIG for the calibration trigger.
Note: If no calibration trigger is needed, leave CAL_TRIG_EN=0 and CAL_SOFT_TRIG=1 (trigger set high).

7.6.24 CAL_LP Register (Address = 0x6E) [reset = 0x88]

CAL_LP is shown in Figure 7-51 and described in Table 7-61.

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Low-Power Background Calibration (default: 0x88)

Figure 7-51 CAL_LP Register
76543210
LP_SLEEP_DLYLP_WAKE_DLYRESERVEDLP_TRIGLP_EN
R/W-0x4R/W-0x1R/W-0x0R/W-0x0R/W-0x0
Table 7-61 CAL_LP Register Field Descriptions
BitFieldTypeResetDescription
7:5LP_SLEEP_DLYR/W0x4

These bits adjust how long an ADC sleeps before waking for calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values below 4 are not recommended because of limited overall power reduction benefits.
0: Sleep delay = (23 + 1) × 256 × tCLK
1: Sleep delay = (215 + 1) × 256 × tCLK
2: Sleep delay = (218 + 1) × 256 × tCLK
3: Sleep delay = (221 + 1) × 256 × tCLK
4: Sleep delay = (224 + 1) × 256 × tCLK (default, approximately 1.338 seconds with a 3.2-GHz clock)
5: Sleep delay = (227 + 1) × 256 × tCLK
6: Sleep delay = (230 + 1) × 256 × tCLK
7: Sleep delay = (233 + 1) × 256 × tCLK

4:3LP_WAKE_DLYR/W0x1

These bits adjust how much time is provided for settling before calibrating an ADC after the ADC wakes up (only applies when LP_EN = 1). Values lower than 1 are not recommended because there is insufficient time for the core to stabilize before calibration begins.
0: Wake delay = (23 + 1) × 256 × tCLK
1: Wake delay = (218 + 1) × 256 × tCLK (default, approximately 21 ms with a 3.2-GHz clock)
2: Wake delay = (221 + 1) × 256 × tCLK
3: Wake delay = (224 + 1) × 256 × tCLK

2RESERVEDR/W0x0
1LP_TRIGR/W0x0

0 : ADC sleep duration is set by LP_SLEEP_DLY (autonomous mode).
1 : ADCs sleep until awoken by a trigger. An ADC is awoken when the calibration trigger is low.

0LP_ENR/W0x0

0 : Disable low-power background calibration (default)
1 : Enable low-power background calibration (only applies when CAL_BG=1).

7.6.25 CAL_DATA_EN Register (Address = 0x70) [reset = 0x00]

CAL_DATA_EN is shown in Figure 7-52 and described in Table 7-62.

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Calibration Data Enable (default: 0x00)

Figure 7-52 CAL_DATA_EN Register
76543210
RESERVEDCAL_DATA_EN
R/W-0x0R/W-0x0
Table 7-62 CAL_DATA_EN Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0
0CAL_DATA_ENR/W0x0

Set this bit to enable the CAL_DATA register to enable reading and writing of calibration data; see the CAL_DATA register for more information.

7.6.26 CAL_DATA Register (Address = 0x71) [reset = 0x0]

CAL_DATA is shown in Figure 7-53 and described in Table 7-63.

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Calibration Data (default: undefined)

Figure 7-53 CAL_DATA Register
76543210
CAL_DATA
R/W-0x0
Table 7-63 CAL_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CAL_DATAR/W0x0

After setting CAL_DATA_EN, repeated reads of this register return all calibration values for the ADCs. Repeated writes of this register input all calibration values for the ADCs. To read the calibration data, read the register 673 times. To write the vector, write the register 673 times with previously stored calibration data. To speed up the read or write operation, set ADDR_HOLD = 1 and use streaming read or write process.

IMPORTANT: Accessing the CAL_DATA register when CAL_STOPPED = 0 corrupts the calibration. Also, stopping the process before reading or writing 673 times leaves the calibration data in an invalid state.

7.6.27 GAIN_TRIM_A Register (Address = 0x7A) [reset = 0x0]

GAIN_TRIM_A is shown in Figure 7-54 and described in Table 7-64.

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Gain DAC Trim A (default from Fuse ROM)

Figure 7-54 GAIN_TRIM_A Register
76543210
GAIN_TRIM_A
R/W-0x0
Table 7-64 GAIN_TRIM_A Register Field Descriptions
BitFieldTypeResetDescription
7:0GAIN_TRIM_AR/W0x0

This register enables gain trim of INA±. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_A to adjust the analog full-scale voltage (Vfs) of INA±.

7.6.28 GAIN_TRIM_B Register (Address = 0x7B) [reset = 0x0]

GAIN_TRIM_B is shown in Figure 7-55 and described in Table 7-65.

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Gain DAC Trim B (default from Fuse ROM)

Figure 7-55 GAIN_TRIM_B Register
76543210
GAIN_TRIM_B
R/W-0x0
Table 7-65 GAIN_TRIM_B Register Field Descriptions
BitFieldTypeResetDescription
7:0GAIN_TRIM_BR/W0x0

This register enables gain trim of INB±. After reset, the factory trimmed value can be read and adjusted as required. Use FS_RANGE_B to adjust the analog full-scale voltage (Vfs) of INB±.

7.6.29 BG_TRIM Register (Address = 0x7C) [reset = 0x0]

BG_TRIM is shown in Figure 7-56 and described in Table 7-66.

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Band-Gap Trim (default from Fuse ROM)

Figure 7-56 BG_TRIM Register
76543210
RESERVEDBG_TRIM
R/W-0x0R/W-0x0
Table 7-66 BG_TRIM Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0
3:0BG_TRIMR/W0x0

This register enables trimming of the internal band-gap reference. After reset, the factory trimmed value can be read and adjusted as required.

7.6.30 RTRIM_A Register (Address = 0x7E) [reset = 0x0]

RTRIM_A is shown in Figure 7-57 and described in Table 7-67.

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Resistor Trim for VinA (default from Fuse ROM)

Figure 7-57 RTRIM_A Register
76543210
RTRIM_A
R/W-0x0
Table 7-67 RTRIM_A Register Field Descriptions
BitFieldTypeResetDescription
7:0RTRIM_AR/W0x0

This register controls the INA± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

7.6.31 RTRIM_B Register (Address = 0x7F) [reset = 0x0]

RTRIM_B is shown in Figure 7-58 and described in Table 7-68.

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Resistor Trim for VinB (default from Fuse ROM)

Figure 7-58 RTRIM_B Register
76543210
RTRIM_B
R/W-0x0
Table 7-68 RTRIM_B Register Field Descriptions
BitFieldTypeResetDescription
7:0RTRIM_BR/W0x0

This register controls the INB± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

7.6.32 ADC_DITH Register (Address = 0x9D) [reset = 0x01]

ADC_DITH is shown in Figure 7-59 and described in Table 7-69.

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ADC Dither Control (default from Fuse ROM)

Figure 7-59 ADC_DITH Register
76543210
RESERVEDADC_DITH_ERRADC_DITH_AMPADC_DITH_EN
R/W-0x0R/W-0x0R/W-0x0R/W-0x1
Table 7-69 ADC_DITH Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR/W0x0
2ADC_DITH_ERRR/W0x0

Small rounding errors may occur when subtracting the dither signal. The error can be chosen to either slightly degrade SNR or to slightly increase the DC offset and FS/2 spur. In addition, the FS/4 spur will also be increased slightly while in single channel mode.
0 : Rounding error degrades SNR
1 : Rounding error degrades DC offset, FS/2 spur and FS/4 spur

1ADC_DITH_AMPR/W0x0

0 : Small dither for better SNR (default)
1 : Large dither for better spurious performance

0ADC_DITH_ENR/W0x1

Set this bit to enable ADC dither. Dither can improve spurious performance at the expense of slightly degraded SNR. The dither amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR and spurious performance.

7.6.33 LSB_CTRL Register (Address = 0x160) [reset = 0x00]

LSB_CTRL is shown in Figure 7-60 and described in Table 7-70.

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LSB Control Bit Output (default: 0x00)

Figure 7-60 LSB_CTRL Register
76543210
RESERVEDTIME_STAMP_EN
R/W-0x0R/W-0x0
Table 7-70 LSB_CTRL Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0
0TIME_STAMP_ENR/W0x0

When set, the timestamp signal is transmitted on the LSB of the output samples. The latency of the timestamp signal (through the entire chip) matches the latency of the analog ADC inputs. Also set SYNC_RECV_EN when using TIME_STAMP_EN.

Note 1: In 8-bit modes, the control bit is placed on the LSB of the 8-bit samples (leaving 7-bits of sample data). If the part is configured for 12-bit data, the control bit is placed on the LSB of the 12-bit bit data (leaving 11-bits of sample data).
Note 2: The control bit that is enabled by this register is never advertised in the ILA (CS is 0 in the ILA).

7.6.34 JESD_EN Register (Address = 0x200) [reset = 0x01]

JESD_EN is shown in Figure 7-61 and described in Table 7-71.

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JESD204C Subsystem Enable (default: 0x01)

Figure 7-61 JESD_EN Register
76543210
RESERVEDJESD_EN
R/W-0x0R/W-0x1
Table 7-71 JESD_EN Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0
0JESD_ENR/W0x1

0 : Disable JESD204C interface
1 : Enable JESD204C interface

Note: Before altering other JESD204C registers, you must clear JESD_EN. When JESD_EN is 0, the block is held in reset and the serializers are powered down. The clocks are gated off to save power. The LMFC/LEMC counter is also held in reset, so SYSREF will not align the LMFC/LEMC.

Note 2: Always set CAL_EN before setting JESD_EN.
Note 3: Always clear JESD_EN before clearing CAL_EN.

7.6.35 JMODE Register (Address = 0x201) [reset = 0x02]

JMODE is shown in Figure 7-62 and described in Table 7-72.

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JESD204C Mode (default: 0x02)

Figure 7-62 JMODE Register
76543210
RW
Table 7-72 JMODE Register Field Descriptions
BitFieldTypeResetDescription
7:0JMODERW0x02

Specify the JESD204C Modes (including DDC decimation factor)

Note 1: This register should only be changed when JESD_EN=0 and CAL_EN=0.

Note 2: The MODE_LOCK register determines which modes are allowed.

7.6.36 KM1 Register (Address = 0x202) [reset = 0x1F]

KM1 is shown in Figure 7-63 and described in Table 7-73.

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JESD204C K Parameter (default: 0x1F)

Figure 7-63 KM1 Register
76543210
KM1
R/W-0x1F
Table 7-73 KM1 Register Field Descriptions
BitFieldTypeResetDescription
7:0KM1R/W0x1F

K is the number of frames per multiframe and this register must be programmed as K-1. Depending on the JMODE setting, there are constraints on the legal values of K (see KR).
The default values is KM1=31, which corresponds to K=32.

Note: For modes using the 64b/66b link layer, the KM1 register is ignored and the value of K is determined from JMODE. The effective value of K is 256*E/F.

Note: This register should only be changed when JESD_EN is 0.

7.6.37 JSYNC_N Register (Address = 0x203) [reset = 0x01]

JSYNC_N is shown in Figure 7-64 and described in Table 7-74.

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JESD204C Manual Sync Request (default: 0x01)

Figure 7-64 JSYNC_N Register
76543210
RESERVEDJSYNC_N
R/W-0x0R/W-0x1
Table 7-74 JSYNC_N Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0
0JSYNC_NR/W0x1

Set this bit to 0 to request JESD204C synchronization (equivalent to the SYNC~ signal being asserted). For normal operation, leave this bit set to 1.

Note: The JSYNC_N register can always generate a synchronization request, regardless of the SYNC_SEL register. However, if the selected sync pin is stuck low, you cannot de-assert the synchronization request unless you program SYNC_SEL=2.

7.6.38 JCTRL Register (Address = 0x204) [reset = 0x03]

JCTRL is shown in Figure 7-65 and described in Table 7-75.

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JESD204C Control (default: 0x03)

Figure 7-65 JCTRL Register
76543210
RESERVEDALT_LANESSYNC_SELSFORMATSCR
R/W-0x0R/W-0x0R/W-0x0R/W-0x1R/W-0x1
Table 7-75 JCTRL Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4ALT_LANESR/W0x0

0 : Normal lane mapping (default). Link A uses lanes DA0 to DA3 and link B uses lanes DB0 to DB3. Other lanes are powered down.
1 : Alternate lane mapping (use upper lanes). Link A uses lanes DA4 to DA7 and link B uses lanes DB4 to DB7. Lanes DA0 to DA3 and DB0 to DB3 are powered down.

Note: This option is only supported when JMODE selects a mode that uses 8 or less lanes. The behavior is undefined for modes that do not meet this requirement.

3:2SYNC_SELR/W0x0

0 : Use the SYNCSE input for SYNC~ function (default)
1 : Use the TMSTP input for SYNC~ function. TMSTP_RECV_EN must also be set.
2 : Do not use any sync input pin (use software SYNC~ through JSYNC_N)

1SFORMATR/W0x1

Output sample format for JESD204C samples
0 : Offset binary
1 : Signed 2’s complement (default)

0SCRR/W0x1

0 : 8B/10B Scrambler disabled (applies only to 8B/10B modes)
1 : 8b/10b Scrambler enabled (default)

Note 1: 64B/66B modes always use scrambling. This register does not apply to 64B/66B modes.

Note 2: This register should only be changed when JESD_EN is 0.

7.6.39 JTEST Register (Address = 0x205) [reset = 0x00]

JTEST is shown in Figure 7-66 and described in Table 7-76.

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JESD204C Test Control (default: 0x00)

Figure 7-66 JTEST Register
76543210
RESERVEDJTEST
R/W-0x0R/W-0x0
Table 7-76 JTEST Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4:0JTESTR/W0x0

0 : Test mode disabled. Normal operation (default)
1 : PRBS7 test mode
2 : PRBS15 test mode
3 : PRBS23 test mode
4 : Ramp test mode
5 : Transport Layer test mode
6 : D21.5 test mode
7 : K28.5 test mode*
8 : Repeated ILA test mode*
9 : Modified RPAT test mode*
10: Serial outputs held low
11: Serial outputs held high
12: RESERVED
13: PRBS9 test mode
14: PRBS31 test mode
15: Clock test pattern (0x00FF)
16: K28.7 test mode*
17-31: RESERVED

* These test modes are only supported when JMODE is selecting a mode that uses 8b/10b encoding.
Note: This register should only be changed when JESD_EN is 0.

7.6.40 DID Register (Address = 0x206) [reset = 0x00]

DID is shown in Figure 7-67 and described in Table 7-77.

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JESD204C DID Parameter (default: 0x00)

Figure 7-67 DID Register
76543210
DID
R/W-0x0
Table 7-77 DID Register Field Descriptions
BitFieldTypeResetDescription
7:0DIDR/W0x0

Specifies the DID (Device ID) value that is transmitted during the second multiframe of the JESD204B ILA. Link A will transmit DID, and link B will transmit DID+1. Bit 0 is ignored and always returns 0 (if you program an odd number, it will be decremented to an even number).

Note: This register should only be changed when JESD_EN is 0.

7.6.41 FCHAR Register (Address = 0x207) [reset = 0x00]

FCHAR is shown in Figure 7-68 and described in Table 7-78.

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JESD204C Frame Character (default: 0x00)

Figure 7-68 FCHAR Register
76543210
RESERVEDFCHAR
R/W-0x0R/W-0x0
Table 7-78 FCHAR Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0
1:0FCHARR/W0x0

Specify which comma character is used to denote end-of-frame. This character is transmitted opportunistically. This only applies to modes that use 8B/10B encoding.
0 : Use K28.7 (default) (JESD204C compliant)
1 : Use K28.1 (not JESD204C compliant)
2 : Use K28.5 (not JESD204C compliant)
3 : Reserved

When using a JESD204C receiver, always use FCHAR=0.
When using a general purpose 8B/10B receiver, the K28.7 character may cause issues. When K28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers will re-align to the false comma. To avoid this, program FCHAR to 1 or 2.

Note: This register should only be changed when JESD_EN is 0.

7.6.42 JESD_STATUS Register (Address = 0x208) [reset = 0x0]

JESD_STATUS is shown in Figure 7-69 and described in Table 7-79.

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JESD204C / System Status Register

Figure 7-69 JESD_STATUS Register
76543210
RESERVEDLINK_UPSYNC_STATUSREALIGNEDALIGNEDPLL_LOCKEDRESERVED
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 7-79 JESD_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0
6LINK_UPR/W0x0

When set, indicates that the JESD204C link is up.

5SYNC_STATUSR/W0x0

Returns the state of the JESD204C SYNC~ signal.
0 : SYNC~ asserted
1 : SYNC~ de-asserted

4REALIGNEDR/W0x0

When high, indicates that the digital block clock, frame clock, or multiframe (LMFC) clock phase was realigned by SYSREF. Writing a 1 to this bit will clear it.

3ALIGNEDR/W0x0

When high, indicates that the multiframe (LMFC) clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Writing a 1 to this bit will clear it.

2PLL_LOCKEDR/W0x0

When high, indicates that the serializer PLL is locked.

1:0RESERVEDR/W0x0

7.6.43 PD_CH Register (Address = 0x209) [reset = 0x00]

PD_CH is shown in Figure 7-70 and described in Table 7-80.

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JESD204C Channel Power Down (default: 0x00)

Figure 7-70 PD_CH Register
76543210
RESERVEDPD_BCHPD_ACH
R/W-0x0R/W-0x0R/W-0x0
Table 7-80 PD_CH Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0
1PD_BCHR/W0x0

When set, the “B” ADC channel is powered down. The digital channels that are bound to the “B” ADC channel are also powered down (see DIG_BIND).

Important notes:
1. You must set JESD_EN=0 before changing PD_CH.
2. To power down both ADC channels, use the MODE register.
3. If both channels are powered down, then the entire JESD204C subsystem is powered down, including serializer PLL and LMFC.
4. If the selected JESD204C mode transmits A and B data on link A, and the B digital channel is disabled, link A remains operational, but the B-channel samples are undefined. For proper operation in foreground calibration mode, ADC_OFF in the CAL_CFG register should be programmed to 0x1.

0PD_ACHR/W0x0

When set, the “A” ADC channel is powered down. The digital channels that are bound to the “A” ADC channel are also powered down (see DIG_BIND).

Important notes:
1. You must set JESD_EN=0 before changing PD_CH.
2. To power down both ADC channels, use the MODE register.
3. If both channels are powered down, then the entire JESD204C subsystem is powered down, including serializer PLL and LMFC.
4. If the selected JESD204C mode transmits A and B data on link A, and the B digital channel is disabled, link A remains operational, but the B-channel samples are undefined. For proper operation in foreground calibration mode, ADC_OFF in the CAL_CFG register should be programmed to 0x1.

7.6.44 JEXTRA_A Register (Address = 0x20A) [reset = 0x00]

JEXTRA_A is shown in Figure 7-71 and described in Table 7-81.

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JESD204C Extra Lane Enable (Link A) (default: 0x00)

Figure 7-71 JEXTRA_A Register
76543210
EXTRA_LANE_AEXTRA_SER_A
R/W-0x0R/W-0x0
Table 7-81 JEXTRA_A Register Field Descriptions
BitFieldTypeResetDescription
7:1EXTRA_LANE_AR/W0x0

Program these register bits to enable extra lanes (even if the selected JMODE does not require the lanes to be enabled). EXTRA_LANE_A(n) enables An (n=1 to 7). This register enables the link layer clocks for the affected lanes. To also enable the extra serializes set EXTRA_SER_A=1.

0EXTRA_SER_AR/W0x0

0 : Only the link layer clocks for extra lanes are enabled.
1 : Serializers for extra lanes are enabled (as well as link layer clocks). Use this mode to transmit data from the extra lanes.

Important Notes:
1. This register should only be changed when JESD_EN is 0.
2. The bit-rate and mode of the extra lanes are set by JMODE and JTEST (see exception below).
3. If a lane is enabled by this register (and was not enabled by JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp (same as JTEST=4).
4. This register does not override the PD_CH register, so make sure the link is enabled to use this feature.
5. To enable serializer 'n', the lower number lanes 0 to n-1 must also be enabled, otherwise serializer 'n' will not receive a clock.

7.6.45 JEXTRA_B Register (Address = 0x20B) [reset = 0x00]

JEXTRA_B is shown in Figure 7-72 and described in Table 7-82.

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JESD204C Extra Lane Enable (Link B) (default: 0x00)

Figure 7-72 JEXTRA_B Register
76543210
EXTRA_LANE_BEXTRA_SER_B
R/W-0x0R/W-0x0
Table 7-82 JEXTRA_B Register Field Descriptions
BitFieldTypeResetDescription
7:1EXTRA_LANE_BR/W0x0

Program these register bits to enable extra lanes (even if the selected JMODE does not require the lanes to be enabled). EXTRA_LANE_B(n) enables Bn (n=1 to 7). This register enables the link layer clocks for the affected lanes. To also enable the extra serializes set EXTRA_SER_B=1.

0EXTRA_SER_BR/W0x0

0 : Only the link layer clocks for extra lanes are enabled.
1 : Serializers for extra lanes are enabled (as well as link layer clocks). Use this mode to transmit data from the extra lanes.

Important Notes:
1. This register should only be changed when JESD_EN is 0.
2. The bit-rate and mode of the extra lanes are set by JMODE and JTEST (see exception below).
3. If a lane is enabled by this register (and was not enabled by JMODE), and JTEST is 0 or 5, the extra lanes will use an octet ramp (same as JTEST=4).
4. This register does not override the PD_CH register, so make sure that the link is enabled to use this feature.
5. To enable serializer 'n', the lower number lanes 0 to n-1 must also be enabled, otherwise serializer 'n' will not receive a clock.

7.6.46 SHMODE Register (Address = 0x20F) [reset = 0x00]

SHMODE is shown in Figure 7-73 and described in Table 7-83.

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JESD204C Sync Word Mode (default: 0x00)

Figure 7-73 SHMODE Register
76543210
RESERVEDSHMODE
R/W-0x0R/W-0x0
Table 7-83 SHMODE Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0
1:0SHMODER/W0x0

Select the mode for the 64b/66b sync word (32 bits of data per multi-block). This only applies when JMODE is selecting a 64b/66b mode.

0 : Transmit CRC-12 signal (default setting)
1 : RESERVED
2 : Transmit FEC signal
3 : RESERVED

Note: This device does not support any JESD204C command features. All command fields will be set to zero (idle headers).
Note: This register should only be changed when JESD_EN is 0.

7.6.47 DDC_CFG Register (Address = 0x210) [reset = 0x00]

DDC_CFG is shown in Figure 7-74 and described in Table 7-84.

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DDC Configuration (default: 0x00)

Figure 7-74 DDC_CFG Register
76543210
RESERVEDBOOST
R/W-0x0R/W-0x0
Table 7-84 DDC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0
0BOOSTR/W0x0

DDC gain control.
0 : DDC filter has 0dB gain (default).
1 : DDC filter has 6.02dB gain. Only use this setting when you are certain the negative image of your input signal is filtered out by the DDC, otherwise clipping may occur.

7.6.48 OVR_T0 Register (Address = 0x211) [reset = 0xF2]

OVR_T0 is shown in Figure 7-75 and described in Table 7-85.

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Over-range Threshold 0 (default: 0xF2)

Figure 7-75 OVR_T0 Register
76543210
OVR_T0
R/W-0xF2
Table 7-85 OVR_T0 Register Field Descriptions
BitFieldTypeResetDescription
7:0OVR_T0R/W0xF2

This parameter defines the absolute sample level that causes control bit 0 to be set. Control bit 0 is attached to the DDC I output samples. The detection level in dBFS (peak) is 20log10(OVR_T0/256) (Default: 0xF2 = 242-> -0.5dBFS)

7.6.49 OVR_T1 Register (Address = 0x212) [reset = 0xAB]

OVR_T1 is shown in Figure 7-76 and described in Table 7-86.

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Over-range Threshold 1 (default: 0xAB)

Figure 7-76 OVR_T1 Register
76543210
OVR_T1
R/W-0xAB
Table 7-86 OVR_T1 Register Field Descriptions
BitFieldTypeResetDescription
7:0OVR_T1R/W0xAB

This parameter defines the absolute sample level that causes control bit 1 to be set. Control bit 1 is attached to the DDC Q output samples. The detection level in dBFS (peak) is 20log10(OVR_T1/256) (Default: 0xAB = 171 -> -3.5dBFS)

7.6.50 OVR_CFG Register (Address = 0x213) [reset = 0x07]

OVR_CFG is shown in Figure 7-77 and described in Table 7-87.

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Over-range Enable / Hold Off (default: 0x07)

Figure 7-77 OVR_CFG Register
76543210
RESERVEDOVR_ENOVR_N
R/W-0x0R/W-0x0R/W-0x7
Table 7-87 OVR_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0
3OVR_ENR/W0x0

Enables over-range status output pins when set high. The ORA0, ORA1, ORB0 and ORB1 outputs are held low when OVR_EN is set low. This register only affects the over-range output pins (ORxx). JESD204C modes that transmit over-range bits are not affected by this register.

2:0OVR_NR/W0x7

Program this register to adjust the pulse extension for the ORA0/1 and ORB0/1 outputs. The minimum pulse duration of the over-range outputs is 8 * 2OVR_N DEVCLK cycles. Incrementing this field doubles the monitoring period.

7.6.51 CMODE Register (Address = 0x214) [reset = 0x00]

CMODE is shown in Figure 7-78 and described in Table 7-88.

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DDC NCO Configuration Preset Mode (default: 0x00)

Figure 7-78 CMODE Register
76543210
RESERVEDCMODE
R/W-0x0R/W-0x0
Table 7-88 CMODE Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0
1:0CMODER/W0x0

This register sets the selection mode for the NCO frequency used in the DDC block. The NCO frequency and phase for DDC A are set by the FREQAx and PHASEAx registers and the NCO frequency and phase for DDC B are set by the FREQBx and PHASEBx registers, where x is the configuration preset (0 through 3). In single channel mode, the NCO selection method for DDC A in dual channel mode is used to set the NCO for the single channel DDC.

0: Use CSEL register to select the active NCO configuration preset for DDC A and DDC B
1: Use NCOA[1:0] pins to select the active NCO configuration preset for DDC A and use NCOB[1:0] pins to select the active NCO configuration preset for DDC B
2: Use NCOA[1:0] pins to select the active NCO configuration preset for both DDC A and DDC B
3: RESERVED

7.6.52 CSEL Register (Address = 0x215) [reset = 0x00]

CSEL is shown in Figure 7-79 and described in Table 7-89.

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DDC NCO Configuration Preset Select (default: 0x00)

Figure 7-79 CSEL Register
76543210
RESERVEDCSELBCSELA
R/W-0x0R/W-0x0R/W-0x0
Table 7-89 CSEL Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0
3:2CSELBR/W0x0

When CMODE=0, this register is used to select the active NCO configuration preset for DDC B In single channel mode, this register is ignored and CSELA must be used instead.

1:0CSELAR/W0x0

When CMODE=0, this register is used to select the active NCO configuration preset for DDC A Example: If CSELA=0, then FREQA0 and PHASEA0 are the active settings. If CSELA=1, then FREQA1 and PHASEA1 are the active settings.

In single channel mode CSELA selects the NCO frequency for the DDC.

7.6.53 DIG_BIND Register (Address = 0x216) [reset = 0x02]

DIG_BIND is shown in Figure 7-80 and described in Table 7-90.

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Digital Channel Binding (default: 0x02)

Figure 7-80 DIG_BIND Register
76543210
RESERVEDDIG_BIND[1]DIG_BIND[0]
R/W-0x0R/W-0x1R/W-0x0
Table 7-90 DIG_BIND Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0
1DIG_BIND[1]R/W0x1

Digital channel B input select:
0: Digital channel B receives data from ADC channel A
1: Digital channel B receives data from ADC channel B (default)

0DIG_BIND[0]R/W0x0

Digital channel A input select:
0: Digital channel A receives data from ADC channel A (default)
1: Digital channel A receives data from ADC channel B

Note 1: When using single channel mode, you must always use the default setting for DIG_BIND or the device will not work.
Note 2: You must set JESD_EN=0 and CAL_EN=0 before changing DIG_BIND.
Note 3: The DIG_BIND setting is combined with PD_ACH/PD_BCH to determine if a digital channel is powered down. Each digital channel (and link) is powered down when the ADC channel it is bound to is powered down (by PD_ACH/PD_BCH).

7.6.54 NCO_RDIV Register (Address = 0x217) [reset = 0x0000]

NCO_RDIV is shown in Figure 7-81 and described in Table 7-91.

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NCO Reference Divisor (default: 0x0000)

Figure 7-81 NCO_RDIV Register
15141312111098
NCO_RDIV
R/W-0x0
76543210
NCO_RDIV
R/W-0x0
Table 7-91 NCO_RDIV Register Field Descriptions
BitFieldTypeResetDescription
15:0NCO_RDIVR/W0x0

Sometimes the 32-bit NCO frequency word does not provide the desired frequency step size and can only approximate the desired frequency. This results in a frequency error. Use this register to eliminate the frequency error.

The default value of 0 disables the reference divisor and the NCO operates as a traditional 32-bit NCO.

Any combination of FS and FSTEP that results in a fractional value for NCO_RDIV is not supported. Values of NCO_RDIV larger than 8192 may degrade the NCO’s SFDR performance and are not recommended. This register is used for all NCO configuration presets.

7.6.55 NCO_SYNC Register (Address = 0x219) [reset = 0x02]

NCO_SYNC is shown in Figure 7-82 and described in Table 7-92.

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NCO Synchronization (default: 0x02)

Figure 7-82 NCO_SYNC Register
76543210
RESERVEDNCO_SYNC_ILANCO_SYNC_NEXT
R/W-0x0R/W-0x1R/W-0x0
Table 7-92 NCO_SYNC Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0
1NCO_SYNC_ILAR/W0x1

When this bit is set, the NCO phase is initialized on the LMFC/LEMC boundary immediately after the rising edge of the SYNC~ signal (default). This feature works in 8B/10B and 64B/66B modes. This feature can be used to precisely align the NCO phase in several ADCs. In 64B/66B modes SYNC~ is only used for this purpose and does not affect the link operation.

0NCO_SYNC_NEXTR/W0x0

After writing ‘0’ and then ‘1’ to this bit, the next SYSREF rising edge will initialize the NCO phase. Once the NCO phase has been initialized by SYSREF, the NCO will not re-initialize on future SYSREF edges unless ‘0’ and ‘1’ is written to this bit again.

Use this to align the NCO in multiple parts (without the need to restart the JESD link).
1. Make sure the part is powered up, JESD_EN is set, and the device clock is running.
2. Make sure that SYSREF is disabled (not toggling).
3. Program NCO_SYNC_ILA=0 on all parts.
4. Write NCO_SYNC_NEXT=0 on all parts.
5. Write NCO_SYNC_NEXT=1 on all parts. NCO sync is armed.
6. Instruct the SYSREF source to generate 1 or more SYSREF pulses.
7. All parts will initialize their NCO using the first SYSREF rising edge.

7.6.56 FREQA0 Register (Address = 0x220) [reset = 0xC0000000]

FREQA0 is shown in Figure 7-83 and described in Table 7-93.

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NCO Frequency (Channel A, Preset 0) (default: 0xC0000000)

Figure 7-83 FREQA0 Register
313029282726252423222120191817161514131211109876543210
FREQA0
R/W-0xC0000000
Table 7-93 FREQA0 Register Field Descriptions
BitFieldTypeResetDescription
31:0FREQA0R/W0xC0000000

The following description applies to FREQA0 thru FREQA3 and FREQB0 thru FREQB3.

The NCO frequency (FNCO) is:
FNCO = FREQA0 * 232 * FADC
FADC is the sampling frequency of the ADC. FREQA0 is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid).

Use this equation to determine the value to program:
FREQA0 = 232 * FNCO /FS

If the equation does not result in an integer value, you must choose an alternate frequency step (FSTEP) and program the NCO_RDIV register. Then use one of these equations to compute FREQA0:
FREQA0 = round(232 * FNCO/FS)
FREQA0 = round(225 * FNCO/FSTEP/NCO_RDIV)

Changing this register after the NCO has been synchronized is running will result in non-deterministic NCO phase. If deterministic phase is required, the NCO should be re-synchronized after changing this register.

7.6.57 PHASEA0 Register (Address = 0x224) [reset = 0x0000]

PHASEA0 is shown in Figure 7-84 and described in Table 7-94.

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NCO Phase (Channel A, Preset 0) (default: 0x0000)

Figure 7-84 PHASEA0 Register
15141312111098
PHASEA0
R/W-0x0
76543210
PHASEA0
R/W-0x0
Table 7-94 PHASEA0 Register Field Descriptions
BitFieldTypeResetDescription
15:0PHASEA0R/W0x0

NCO phase for configuration preset 0. This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASEA0 * 2-16 * 2π. This register can be interpreted as signed or unsigned.

7.6.58 FREQA1 Register (Address = 0x228) [reset = 0xC0000000]

FREQA1 is shown in Figure 7-85 and described in Table 7-95.

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NCO Frequency (Channel A, Preset 1) (default: 0xC0000000)

Figure 7-85 FREQA1 Register
313029282726252423222120191817161514131211109876543210
FREQA1
R/W-0xC0000000
Table 7-95 FREQA1 Register Field Descriptions
BitFieldTypeResetDescription
31:0FREQA1R/W0xC0000000

NCO frequency for channel A, NCO preset 1

7.6.59 PHASEA1 Register (Address = 0x22C) [reset = 0x0000]

PHASEA1 is shown in Figure 7-86 and described in Table 7-96.

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NCO Phase (Channel A, Preset 1) (default: 0x0000)

Figure 7-86 PHASEA1 Register
15141312111098
PHASEA1
R/W-0x0
76543210
PHASEA1
R/W-0x0
Table 7-96 PHASEA1 Register Field Descriptions
BitFieldTypeResetDescription
15:0PHASEA1R/W0x0

NCO phase for channel A, preset 1

7.6.60 FREQA2 Register (Address = 0x230) [reset = 0xC0000000]

FREQA2 is shown in Figure 7-87 and described in Table 7-97.

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NCO Frequency (Channel A, Preset 2) (default: 0xC0000000)

Figure 7-87 FREQA2 Register
313029282726252423222120191817161514131211109876543210
FREQA2
R/W-0xC0000000
Table 7-97 FREQA2 Register Field Descriptions
BitFieldTypeResetDescription
31:0FREQA2R/W0xC0000000

NCO frequency for channel A, NCO preset 2

7.6.61 PHASEA2 Register (Address = 0x234) [reset = 0x0000]

PHASEA2 is shown in Figure 7-88 and described in Table 7-98.

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NCO Phase (Channel A, Preset 2) (default: 0x0000)

Figure 7-88 PHASEA2 Register
15141312111098
PHASEA2
R/W-0x0
76543210
PHASEA2
R/W-0x0
Table 7-98 PHASEA2 Register Field Descriptions
BitFieldTypeResetDescription
15:0PHASEA2R/W0x0

NCO phase for channel A, preset 2

7.6.62 FREQA3 Register (Address = 0x238) [reset = 0xC0000000]

FREQA3 is shown in Figure 7-89 and described in Table 7-99.

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NCO Frequency (Channel A, Preset 3) (default: 0xC0000000)

Figure 7-89 FREQA3 Register
313029282726252423222120191817161514131211109876543210
FREQA3
R/W-0xC0000000
Table 7-99 FREQA3 Register Field Descriptions
BitFieldTypeResetDescription
31:0FREQA3R/W0xC0000000

NCO frequency for channel A, NCO preset 3

7.6.63 PHASEA3 Register (Address = 0x23C) [reset = 0x0000]

PHASEA3 is shown in Figure 7-90 and described in Table 7-100.

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NCO Phase (Channel A, Preset 3) (default: 0x0000)

Figure 7-90 PHASEA3 Register
15141312111098
PHASEA3
R/W-0x0
76543210
PHASEA3
R/W-0x0
Table 7-100 PHASEA3 Register Field Descriptions
BitFieldTypeResetDescription
15:0PHASEA3R/W0x0

NCO phase for channel A, preset 3

7.6.64 FREQB0 Register (Address = 0x240) [reset = 0xC0000000]

FREQB0 is shown in Figure 7-91 and described in Table 7-101.

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NCO Frequency (Channel B, Preset 0) (default: 0xC0000000)

Figure 7-91 FREQB0 Register
313029282726252423222120191817161514131211109876543210
FREQB0
R/W-0xC0000000
Table 7-101 FREQB0 Register Field Descriptions
BitFieldTypeResetDescription
31:0FREQB0R/W0xC0000000

NCO frequency for channel B, NCO preset 0.
Note: If the ADC is in DES mode, the NCO frequency and phase settings for channel B are ignored. Use the NCO frequency and phase registers for channel A only.

7.6.65 PHASEB0 Register (Address = 0x244) [reset = 0x0000]

PHASEB0 is shown in Figure 7-92 and described in Table 7-102.

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NCO Phase (Channel B, Preset 0) (default: 0x0000)

Figure 7-92 PHASEB0 Register
15141312111098
PHASEB0
R/W-0x0
76543210
PHASEB0
R/W-0x0
Table 7-102 PHASEB0 Register Field Descriptions
BitFieldTypeResetDescription
15:0PHASEB0R/W0x0

NCO phase for channel B, preset 0

7.6.66 FREQB1 Register (Address = 0x248) [reset = 0xC0000000]

FREQB1 is shown in Figure 7-93 and described in Table 7-103.

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NCO Frequency (Channel B, Preset 1) (default: 0xC0000000)

Figure 7-93 FREQB1 Register
313029282726252423222120191817161514131211109876543210
FREQB1
R/W-0xC0000000
Table 7-103 FREQB1 Register Field Descriptions
BitFieldTypeResetDescription
31:0FREQB1R/W0xC0000000

NCO frequency for channel B, NCO preset 1

7.6.67 PHASEB1 Register (Address = 0x24C) [reset = 0x0000]

PHASEB1 is shown in Figure 7-94 and described in Table 7-104.

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NCO Phase (Channel B, Preset 1) (default: 0x0000)

Figure 7-94 PHASEB1 Register
15141312111098
PHASEB1
R/W-0x0
76543210
PHASEB1
R/W-0x0
Table 7-104 PHASEB1 Register Field Descriptions
BitFieldTypeResetDescription
15:0PHASEB1R/W0x0

NCO phase for channel B, preset 1

7.6.68 FREQB2 Register (Address = 0x250) [reset = 0xC0000000]

FREQB2 is shown in Figure 7-95 and described in Table 7-105.

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NCO Frequency (Channel B, Preset 2) (default: 0xC0000000)

Figure 7-95 FREQB2 Register
313029282726252423222120191817161514131211109876543210
FREQB2
R/W-0xC0000000
Table 7-105 FREQB2 Register Field Descriptions
BitFieldTypeResetDescription
31:0FREQB2R/W0xC0000000

NCO frequency for channel B, NCO preset 2

7.6.69 PHASEB2 Register (Address = 0x254) [reset = 0x0000]

PHASEB2 is shown in Figure 7-96 and described in Table 7-106.

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NCO Phase (Channel B, Preset 2) (default: 0x0000)

Figure 7-96 PHASEB2 Register
15141312111098
PHASEB2
R/W-0x0
76543210
PHASEB2
R/W-0x0
Table 7-106 PHASEB2 Register Field Descriptions
BitFieldTypeResetDescription
15:0PHASEB2R/W0x0

NCO phase for channel B, preset 2

7.6.70 FREQB3 Register (Address = 0x258) [reset = 0xC0000000]

FREQB3 is shown in Figure 7-97 and described in Table 7-107.

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NCO Frequency (Channel B, Preset 3) (default: 0xC0000000)

Figure 7-97 FREQB3 Register
313029282726252423222120191817161514131211109876543210
FREQB3
R/W-0xC0000000
Table 7-107 FREQB3 Register Field Descriptions
BitFieldTypeResetDescription
31:0FREQB3R/W0xC0000000

NCO frequency for channel B, NCO preset 3

7.6.71 PHASEB3 Register (Address = 0x25C) [reset = 0x0000]

PHASEB3 is shown in Figure 7-98 and described in Table 7-108.

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NCO Phase (Channel B, Preset 3) (default: 0x0000)

Figure 7-98 PHASEB3 Register
15141312111098
PHASEB3
R/W-0x0
76543210
PHASEB3
R/W-0x0
Table 7-108 PHASEB3 Register Field Descriptions
BitFieldTypeResetDescription
15:0PHASEB3R/W0x0

NCO phase for channel B, preset 3

7.6.72 INIT_STATUS Register (Address = 0x270) [reset = undefined]

INIT_STATUS is shown in Figure 7-99 and described in Table 7-109.

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Chip Spin Identifier (default: See description, read-only)

Figure 7-99 INIT_STATUS Register
76543210
RESERVEDINIT_STATUS
R-undefinedR-undefined
Table 7-109 INIT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDRundefinedRESERVED
0INIT_DONERundefinedReturns 1 when the initialization logic has finished initializing the device. This indicates that it is now safe to proceed with startup. No SPI transactions should be performed before INIT_DONE returns 1(except SOFT_RESET).

7.6.73 SPIN_ID Register (Address = 0x297) [reset = 0x00]

SPIN_ID is shown in Figure 7-100 and described in Table 7-110.

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Chip Spin Identifier (default: See description, read-only)

Figure 7-100 SPIN_ID Register
76543210
RESERVEDSPIN_ID
R/W-0x0R/W-0x00
Table 7-110 SPIN_ID Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4:0SPIN_IDR/W

0x0

Spin identification value:

0: ADC12DJ5200RF

2 : ADC12DJ4000RF

10: ADC08DJ5200RF

7.6.74 TESTBUS Register (Address = 0x2A2) [reset = 0x0]

TESTBUS is shown in Figure 7-101 and described in Table 7-111.

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TESTBUS Register (default: 0x0)

Figure 7-101 TESTBUS Register
76543210
RESERVEDEN_VD11_NOISE_SUPPREN_VS11_NOISE_SUPPRRESERVED
R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 7-111 TESTBUS Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR/W0x0RESERVED
5EN_VD11_NOISE_SUPPRR/W0x0

When set, noise on VD11 is suppressed. It is recommended to have this set, as it reduces noise coupling from the digital circuits to analog clock, at the expense of a small increase in power.

4EN_VS11_NOISE_SUPPRR/W

When set, noise on VS11 is suppressed. It is recommended to have this set, as it reduces noise coupling from the digital circuits to analog clock, at the expense of a small increase in power.

3:0RESERVEDR/WR/WRESERVED

7.6.75 SRC_EN Register (Address = 0x2B0) [reset = 0x00]

SRC_EN is shown in Figure 7-102 and described in Table 7-112.

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SYSREF Calibration Enable (default: 0x00)

Figure 7-102 SRC_EN Register
76543210
RESERVEDSRC_EN
R/W-0x0R/W-0x0
Table 7-112 SRC_EN Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR/W0x0
0SRC_ENR/W0x0

0: SYSREF Calibration Disabled. Use the TAD register to manually control the tad[16:0] output and adjust the DEVCLK delay. (default)
1: SYSREF Calibration Enabled. The DEVCLK delay is automatically calibrated. The TAD register is ignored.

A 0-to-1 transition on SRC_EN starts the SYSREF calibration sequence. Program SRC_CFG before setting SRC_EN. Make sure that ADC calibration is not currently running before setting SRC_EN.

7.6.76 SRC_CFG Register (Address = 0x2B1) [reset = 0x05]

SRC_CFG is shown in Figure 7-103 and described in Table 7-113.

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SYSREF Calibration Configuration (default: 0x05)

Figure 7-103 SRC_CFG Register
76543210
RESERVEDSRC_AVGSRC_HDUR
R/W-0x0R/W-0x1R/W-0x1
Table 7-113 SRC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR/W0x0
3:2SRC_AVGR/W0x1

Specifies the amount of averaging used for SYSREF Calibration. Larger values will increase calibration time and reduce the variance of the calibrated value.
0: 4 averages
1: 16 averages
2: 64 averages
3: 256 averages

1:0SRC_HDURR/W0x1

Specifies the duration of each high-speed accumulation for SYSREF Calibration. If the SYSREF period exceeds the supported value, calibration will fail. Larger values will increase calibration time and support longer SYSREF periods. For a given SYSREF period, larger values will also reduce the variance of the calibrated value.
0: 4 cycles per accumulation, max SYSREF period of 128 DEVCLK cycles
1: 16 cycles per accumulation, max SYSREF period of 1664 DEVCLK cycles
2: 64 cycles per accumulation, max SYSREF period of 7808 DEVCLK cycles
3: 256 cycles per accumulation, max SYSREF period of 32384 DEVCLK cycles

Max duration of SYSREF calibration is bounded by: TSYSREFCAL (in DEVCLK cycles) = 384 * 19 * 4^(SRC_AVG + SRC_HDUR + 2)

7.6.77 SRC_STATUS Register (Address = 0x2B2) [reset = 0x0]

SRC_STATUS is shown in Figure 7-104 and described in Table 7-114.

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SYSREF Calibration Status (read-only, default: undefined)

Figure 7-104 SRC_STATUS Register
2322212019181716
RESERVEDSRC_DONESRC_TAD
R/W-0x0R/W-0x0R/W-0x0
15141312111098
SRC_TAD
R/W-0x0
76543210
SRC_TAD
R/W-0x0
Table 7-114 SRC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
23:18RESERVEDR/W0x0
17SRC_DONER/W0x0

This bit returns ‘1’ when SRC_EN=1 and SYSREF Calibration has been completed.

16:0SRC_TADR/W0x0

This field returns the value for TAD[16:0] computed by SYSREF Calibration. It is only valid if SRC_DONE=1.

SRC_TAD[16] indicates if DEVCLK has been inverted.
SRC_TAD[15:8] indicates the coarse delay adjustment.
SRC_TAD[7:0] indicates the fine delay adjustment.

7.6.78 TAD Register (Address = 0x2B5) [reset = 0x00]

TAD is shown in Figure 7-105 and described in Table 7-115.

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DEVCLK Timing Adjust (default: 0x00)

Figure 7-105 TAD Register
2322212019181716
RESERVEDTAD_INV
R/W-0x0R/W-0x0
15141312111098
TAD_COARSE
R/W-0x0
76543210
TAD_FINE
R-0x0
Table 7-115 TAD Register Field Descriptions
BitFieldTypeResetDescription
23:17RESERVEDR/W0x0
16TAD_INVR/W0x0

Inverts the sampling clock when set.

15:8TAD_COARSER/W0x0

This register controls the coarse resolution of the sampling aperture delay adjustment when SRC_EN=0. Use this register to manually control the DEVCLK aperture delay when SYSREF Calibration is disabled. If ADC calibration or JESD204B is running, it is recommended that you gradually increase or decrease this value (1 code at a time) to avoid clock glitches. Refer to Switching Characteristics for TAD_COARSE resolution.

If ADC calibration is enabled (CAL_EN=1), or the JESD204C link is enabled (JESD_EN=1), the following rules must be obeyed to avoid clock glitches and unpredictable behavior:
1. Do not change TAD_INV. You must program CAL_EN=0 and JESD_EN=0 before changing TAD_INV.
2. TAD_COARSE must be increased or decreased gradually (no more than 4 codes at a time). This rule can be obeyed manually via SPI writes, or by setting TAD_RAMP_EN.

7:0TAD_FINER/W0x0This register controls the fine resolution of the sampling aperture delay adjustment when SRC_EN=0. Use this register to manually control the DEVCLK aperture delay when SYSREF Calibration is disabled. Refer to Switching Characteristics for TAD_FINE resolution. TAD_FINE may be changed to any value at any time (its adjustment is too fine to cause clock glitches).

7.6.79 TAD_RAMP Register (Address = 0x2B8) [reset = 0x00]

TAD_RAMP is shown in Figure 7-106 and described in Table 7-116.

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DEVCLK Timing Adjust Ramp Control (default: 0x00)

Figure 7-106 TAD_RAMP Register
76543210
RESERVEDTAD_RAMP_RATETAD_RAMP_EN
R/W-0x0R/W-0x0R/W-0x0
Table 7-116 TAD_RAMP Register Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR/W0x0
1TAD_RAMP_RATER/W0x0

Specifies the ramp rate for TAD_COARSE when the TAD_COARSE register is written while TAD_RAMP_EN=1.

0: TAD_COARSE ramps up or down one code per 384 sampling clock cycles.
1: TAD_COARSE ramps up or down 4 codes per 384 sampling clock cycles.

0TAD_RAMP_ENR/W0x0

TAD ramp enable. Set this bit if you want the coarse TAD adjustment (TAD_COARSE) to ramp up or down instead of changing abruptly.
0 : After writing the TAD_COARSE register, the applied TAD_COARSE setting is updated within 1536 CLK cycles (ramp feature disabled).
1 : After writing the TAD_COARSE register, the applied TAD_COARSE setting ramps up or down gradually until it matches the TAD_COARSE register.

7.6.80 ALARM Register (Address = 0x2C0) [reset = 0x0]

ALARM is shown in Figure 7-107 and described in Table 7-117.

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Alarm Interrupt (read-only)

Figure 7-107 ALARM Register
76543210
RESERVEDALARM
R-0x0R-0x0
Table 7-117 ALARM Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0
0ALARMR0x0

This bit returns a ‘1’ whenever any alarm occurs that is unmasked in the ALM_STATUS register. Use ALM_MASK to mask (disable) individual alarms. CAL_STATUS_SEL can be used to drive the ALARM bit onto the CALSTAT output pin to provide a hardware alarm interrupt signal.

7.6.81 ALM_STATUS Register (Address = 0x2C1) [reset = 0x3F]

ALM_STATUS is shown in Figure 7-108 and described in Table 7-118.

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Alarm Status (default: 0x3F, write to clear)

Figure 7-108 ALM_STATUS Register
76543210
RESERVEDFIFO_ALMPLL_ALMLINK_ALMREALIGNED_ALMNCO_ALMCLK_ALM
R/W-0x0R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1
Table 7-118 ALM_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR/W0x0
5FIFO_ALMR/W0x1

FIFO overflow/underflow alarm: This bit is set whenever an active JESD204C lane FIFO experiences an underflow or overflow condition. Write a ‘1’ to clear this bit. To inspect which lane generated the alarm, read FIFO_LANE_ALM.

4PLL_ALMR/W0x1

PLL Lock Lost Alarm: This bit is set whenever the PLL is not locked. Write a ‘1’ to clear this bit.

3LINK_ALMR/W0x1

Link Alarm: This bit is set whenever the JESD204C link is enabled, but is not in the data encoder state (for 8B/10B modes). In 64B/66B modes, there is no data encoder state, so this alarm will be set when the link first starts up, and will also be set if any event causes a FIFO/serializer realignment. Write a ‘1’ to clear this bit.

2REALIGNED_ALMR/W0x1

Realigned Alarm: This bit is set whenever SYSREF causes the internal clocks (including the LMFC/LEMC) to be realigned. Write a ‘1’ to clear this bit.

1NCO_ALMR/W0x1

NCO Alarm: This bit can be used to detect an upset to the NCO phase. This bit is set when any of the following occur:
- The NCOs are disabled (JESD_EN=0).
- The NCOs are synchronized (intentionally or unintentionally)
- Any phase accumulators in channel A do not match channel B.
Write a ‘1’ to clear this bit. Refer to the alarm section for the proper usage of this register.

0CLK_ALMR/W0x1

Clock Alarm: This bit can be used to detect an upset to the internal DDC/JESD204C clocks. This bit is set whenever the internal clock dividers for the A and B channels do not match. Write a ‘1’ to clear this bit. Refer to the alarm section for the proper usage of this register.

Note: After power-on reset or soft-reset, all alarm bits are set to ‘1.’
Note: When JESD_EN=0, all alarms (except CLK_ALM) are undefined. It is recommended that the user clears the alarms after setting JESD_EN=1.

7.6.82 ALM_MASK Register (Address = 0x2C2) [reset = 0x3F]

ALM_MASK is shown in Figure 7-109 and described in Table 7-119.

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Alarm Mask Register (default: 0x3F)

Figure 7-109 ALM_MASK Register
76543210
RESERVEDMASK_FIFO_ALMMASK_PLL_ALMMASK_LINK_ALMMASK_REALIGNED_ALMMASK_NCO_ALMMASK_CLK_ALM
R/W-0x0R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1R/W-0x1
Table 7-119 ALM_MASK Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR/W0x0
5MASK_FIFO_ALMR/W0x1

When set, FIFO_ALM is masked and will not impact the ALARM register bit.

4MASK_PLL_ALMR/W0x1

When set, PLL_ALM is masked and will not impact the ALARM register bit.

3MASK_LINK_ALMR/W0x1

When set, LINK_ALM is masked and will not impact the ALARM register bit.

2MASK_REALIGNED_ALMR/W0x1

When set, REALIGNED_ALM is masked and will not impact the ALARM register bit.

1MASK_NCO_ALMR/W0x1

When set, NCO_ALM is masked and will not impact the ALARM register bit.

0MASK_CLK_ALMR/W0x1

When set, CLK_ALM is masked and will not impact the ALARM register bit.

7.6.83 FIFO_LANE_ALM Register (Address = 0x2C4) [reset = 0xFFFF]

FIFO_LANE_ALM is shown in Figure 7-110 and described in Table 7-120.

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FIFO Overflow/Underflow Alarm (default: 0xFFFF)

Figure 7-110 FIFO_LANE_ALM Register
15141312111098
FIFO_LANE_ALM
R/W-0xFFFF
76543210
FIFO_LANE_ALM
R/W-0xFFFF
Table 7-120 FIFO_LANE_ALM Register Field Descriptions
BitFieldTypeResetDescription
15:0FIFO_LANE_ALMR/W0xFFFF

FIFO_LANE_ALM[i] is set if the FIFO for lane i experiences overflow or underflow. Use this register to determine which lane(s) generated an alarm. Writing a ‘1’ to any bit in this register will clear the alarm (the alarm may immediately trip again if the overflow/underflow condition persists). Writing a ‘1’ to the FIFO_ALM bit in the ALM_STATUS register will clear all bits of this register.

7.6.84 TADJ_A Register (Address = 0x310) [reset = 0x0]

TADJ_A is shown in Figure 7-111 and described in Table 7-121.

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Timing Adjust for A-ADC operating in Dual Channel Mode (default from Fuse ROM)

Figure 7-111 TADJ_A Register
76543210
TADJ_A
R/W-0x0
Table 7-121 TADJ_A Register Field Descriptions
BitFieldTypeResetDescription
7:0TADJ_AR/W0x0

This register (and other TADJ* registers that follow it) are used to adjust the sampling instant of each ADC core. Different TADJ registers apply to different ADCs under different modes. The default values for all TADJ* registers are factory programmed values. The factory trimmed values can be read out and adjusted as required.

7.6.85 TADJ_B Register (Address = 0x313) [reset = 0x0]

TADJ_B is shown in Figure 7-112 and described in Table 7-122.

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Timing Adjust for B-ADC operating in Dual Channel Mode (default from Fuse ROM)

Figure 7-112 TADJ_B Register
76543210
TADJ_B
R/W-0x0
Table 7-122 TADJ_B Register Field Descriptions
BitFieldTypeResetDescription
7:0TADJ_BR/W0x0

See TADJ_A register for description. Adjusts timing of B-ADC in dual channel mode with foreground calibration enabled.

7.6.86 TADJ_A_FG90_VINA Register (Address = 0x314) [reset = 0x0]

TADJ_A_FG90_VINA is shown in Figure 7-113 and described in Table 7-123.

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Timing Adjust for A-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM)

Figure 7-113 TADJ_A_FG90_VINA Register
76543210
TADJ_A_FG90_VINA
R/W-0x0
Table 7-123 TADJ_A_FG90_VINA Register Field Descriptions
BitFieldTypeResetDescription
7:0TADJ_A_FG90_VINAR/W0x0

See TADJ_A register for description. Adjusts timing of A-ADC in single channel mode with foreground calibration enabled and sampling INA±.

7.6.87 TADJ_B_FG0_VINA Register (Address = 0x315) [reset = 0x0]

TADJ_B_FG0_VINA is shown in Figure 7-114 and described in Table 7-124.

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Timing Adjust for B-ADC operating in Single Channel Mode and sampling INA± (default from Fuse ROM)

Figure 7-114 TADJ_B_FG0_VINA Register
76543210
TADJ_B_FG0_VINA
R/W-0x0
Table 7-124 TADJ_B_FG0_VINA Register Field Descriptions
BitFieldTypeResetDescription
7:0TADJ_B_FG0_VINAR/W0x0

See TADJ_A register for description. Adjusts timing of B-ADC in single channel mode with foreground calibration enabled and sampling INA±.

7.6.88 TADJ_A_FG90_VINB Register (Address = 0x31A) [reset = 0x0]

TADJ_A_FG90_VINB is shown in Figure 7-115 and described in Table 7-125.

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Timing Adjust for A-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM)

Figure 7-115 TADJ_A_FG90_VINB Register
76543210
TADJ_A_FG90_VINB
R/W-0x0
Table 7-125 TADJ_A_FG90_VINB Register Field Descriptions
BitFieldTypeResetDescription
7:0TADJ_A_FG90_VINBR/W0x0

See TADJ_A register for description. Adjusts timing of A-ADC in single channel mode with foreground calibration enabled and sampling INB±.

7.6.89 TADJ_B_FG0_VINB Register (Address = 0x31B) [reset = 0x0]

TADJ_B_FG0_VINB is shown in Figure 7-116 and described in Table 7-126.

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Timing Adjust for B-ADC operating in Single Channel Mode and sampling INB± (default from Fuse ROM)

Figure 7-116 TADJ_B_FG0_VINB Register
76543210
TADJ_B_FG0_VINB
R/W-0x0
Table 7-126 TADJ_B_FG0_VINB Register Field Descriptions
BitFieldTypeResetDescription
7:0TADJ_B_FG0_VINBR/W0x0

See TADJ_A register for description. Adjusts timing of B-ADC in single channel mode with foreground calibration enabled and sampling INB±.

7.6.90 OADJ_A_FG0_VINA Register (Address = 0x344) [reset = 0x0]

OADJ_A_FG0_VINA is shown in Figure 7-117 and described in Table 7-127.

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Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INA± (default from Fuse ROM)

Figure 7-117 OADJ_A_FG0_VINA Register
15141312111098
RESERVEDOADJ_A_FG0_VINA
R/W-0x0R/W-0x0
76543210
OADJ_A_FG0_VINA
R/W-0x0
Table 7-127 OADJ_A_FG0_VINA Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0OADJ_A_FG0_VINAR/W0x0

Offset adjustment value applied to A-ADC when it samples INA± in dual channel mode and foreground calibration is enabled.

7.6.91 OADJ_A_FG0_VINB Register (Address = 0x346) [reset = 0x0]

OADJ_A_FG0_VINB is shown in Figure 7-118 and described in Table 7-128.

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Offset Adjustment for A-ADC operating in Dual Channel Mode sampling INB± (default from Fuse ROM)

Figure 7-118 OADJ_A_FG0_VINB Register
15141312111098
RESERVEDOADJ_A_FG_VINB
R/W-0x0R/W-0x0
76543210
OADJ_A_FG_VINB
R/W-0x0
Table 7-128 OADJ_A_FG0_VINB Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0OADJ_A_FG_VINBR/W0x0

Offset adjustment value applied to A-ADC when it samples INB± in dual channel mode and foreground calibration is enabled.

7.6.92 OADJ_A_FG90_VINA Register (Address = 0x348) [reset = 0x0]

OADJ_A_FG90_VINA is shown in Figure 7-119 and described in Table 7-129.

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Offset Adjustment for A-ADC operating in Single Channel Mode sampling INA± (default from Fuse ROM)

Figure 7-119 OADJ_A_FG90_VINA Register
15141312111098
RESERVEDOADJ_A_FG90_VINA
R/W-0x0R/W-0x0
76543210
OADJ_A_FG90_VINA
R/W-0x0
Table 7-129 OADJ_A_FG90_VINA Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0OADJ_A_FG90_VINAR/W0x0

Offset adjustment value applied to A-ADC when it samples INA± in single channel mode and foreground calibration is enabled.

7.6.93 OADJ_A_FG90_VINB Register (Address = 0x34A) [reset = 0x0]

OADJ_A_FG90_VINB is shown in Figure 7-120 and described in Table 7-130.

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Offset Adjustment for A-ADC operating in Single Channel Mode sampling INB± (default from Fuse ROM)

Figure 7-120 OADJ_A_FG90_VINB Register
15141312111098
RESERVEDOADJ_A_FG90_VINB
R/W-0x0R/W-0x0
76543210
OADJ_A_FG90_VINB
R/W-0x0
Table 7-130 OADJ_A_FG90_VINB Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0OADJ_A_FG90_VINBR/W0x0

Offset adjustment value applied to A-ADC when it samples INB± using 90° clock phase and foreground calibration is enabled.

7.6.94 OADJ_B_FG0_VINA Register (Address = 0x34C) [reset = 0x0]

OADJ_B_FG0_VINA is shown in Figure 7-121 and described in Table 7-131.

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Offset Adjustment for B-ADC sampling INA± (default from Fuse ROM)

Figure 7-121 OADJ_B_FG0_VINA Register
15141312111098
RESERVEDOADJ_B_FG0_VINA
R/W-0x0R/W-0x0
76543210
OADJ_B_FG0_VINA
R/W-0x0
Table 7-131 OADJ_B_FG0_VINA Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0OADJ_B_FG0_VINAR/W0x0

Offset adjustment value applied to B-ADC when it samples INA± and foreground calibration is enabled. Applies to both dual channel mode and single channel mode.

7.6.95 OADJ_B_FG0_VINB Register (Address = 0x34E) [reset = 0x0]

OADJ_B_FG0_VINB is shown in Figure 7-122 and described in Table 7-132.

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Offset Adjustment for B-ADC sampling INB± (default from Fuse ROM)

Figure 7-122 OADJ_B_FG0_VINB Register
15141312111098
RESERVEDOADJ_B_FG0_VINB
R/W-0x0R/W-0x0
76543210
OADJ_B_FG0_VINB
R/W-0x0
Table 7-132 OADJ_B_FG0_VINB Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0OADJ_B_FG0_VINBR/W0x0

Offset adjustment value applied to B-ADC when it samples INB± and foreground calibration is enabled. Applies to both dual channel mode and single channel mode.

7.6.96 GAIN_A0_FGDUAL Register (Address = 0x350) [reset = 0x0]

GAIN_A0_FGDUAL is shown in Figure 7-123 and described in Table 7-133.

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Fine Gain Adjust for ADC A Bank 0 in Dual Channel Mode (default from Fuse ROM)

Figure 7-123 GAIN_A0_FGDUAL Register
76543210
RESERVEDGAIN_A0_FGDUAL
R/W-0x0R/W-0x0
Table 7-133 GAIN_A0_FGDUAL Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4:0GAIN_A0_FGDUALR/W0x0

Fine gain adjustment for ADC A bank 0.

7.6.97 GAIN_A1_FGDUAL Register (Address = 0x351) [reset = 0x0]

GAIN_A1_FGDUAL is shown in Figure 7-124 and described in Table 7-134.

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Fine Gain Adjust for ADC A Bank 1 in Dual Channel Mode (default from Fuse ROM)

Figure 7-124 GAIN_A1_FGDUAL Register
76543210
RESERVEDGAIN_A1_FGDUAL
R/W-0x0R/W-0x0
Table 7-134 GAIN_A1_FGDUAL Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4:0GAIN_A1_FGDUALR/W0x0

Fine gain adjustment for ADC A bank 1.

7.6.98 GAIN_B0_FGDUAL Register (Address = 0x352) [reset = 0x0]

GAIN_B0_FGDUAL is shown in Figure 7-125 and described in Table 7-135.

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Fine Gain Adjust for ADC B Bank 0 in Dual Channel Mode (default from Fuse ROM)

Figure 7-125 GAIN_B0_FGDUAL Register
76543210
RESERVEDGAIN_A0_FGDUAL
R/W-0x0R/W-0x0
Table 7-135 GAIN_B0_FGDUAL Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4:0GAIN_A0_FGDUALR/W0x0

Fine gain adjustment for ADC B bank 0.

7.6.99 GAIN_B1_FGDUAL Register (Address = 0x353) [reset = 0x0]

GAIN_B1_FGDUAL is shown in Figure 7-126 and described in Table 7-136.

Return to the Summary Table.

Fine Gain Adjust for ADC B Bank 1 in Dual Channel Mode (default from Fuse ROM)

Figure 7-126 GAIN_B1_FGDUAL Register
76543210
RESERVEDGAIN_B1_FGDUAL
R/W-0x0R/W-0x0
Table 7-136 GAIN_B1_FGDUAL Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4:0GAIN_B1_FGDUALR/W0x0

Fine gain adjustment for ADC B bank 1.

7.6.100 GAIN_A0_FGDES Register (Address = 0x354) [reset = 0x0]

GAIN_A0_FGDES is shown in Figure 7-127 and described in Table 7-137.

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Fine Gain Adjust for ADC A Bank 0 in Single Channel Mode (default from Fuse ROM)

Figure 7-127 GAIN_A0_FGDES Register
76543210
RESERVEDGAIN_A0_FGDUAL
R/W-0x0R/W-0x0
Table 7-137 GAIN_A0_FGDES Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4:0GAIN_A0_FGDUALR/W0x0

Fine gain adjustment for ADC A bank 0.

7.6.101 GAIN_A1_FGDES Register (Address = 0x355) [reset = 0x0]

GAIN_A1_FGDES is shown in Figure 7-128 and described in Table 7-138.

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Fine Gain Adjust for ADC A Bank 1 in Single Channel Mode (default from Fuse ROM)

Figure 7-128 GAIN_A1_FGDES Register
76543210
RESERVEDGAIN_A1_FGDUAL
R/W-0x0R/W-0x0
Table 7-138 GAIN_A1_FGDES Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4:0GAIN_A1_FGDUALR/W0x0

Fine gain adjustment for ADC A bank 1.

7.6.102 GAIN_B0_FGDES Register (Address = 0x356) [reset = 0x0]

GAIN_B0_FGDES is shown in Figure 7-129 and described in Table 7-139.

Return to the Summary Table.

Fine Gain Adjust for ADC B Bank 0 in Single Channel Mode (default from Fuse ROM)

Figure 7-129 GAIN_B0_FGDES Register
76543210
RESERVEDGAIN_A0_FGDUAL
R/W-0x0R/W-0x0
Table 7-139 GAIN_B0_FGDES Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4:0GAIN_A0_FGDUALR/W0x0

Fine gain adjustment for ADC B bank 0.

7.6.103 GAIN_B1_FGDES Register (Address = 0x357) [reset = 0x0]

GAIN_B1_FGDES is shown in Figure 7-130 and described in Table 7-140.

Return to the Summary Table.

Fine Gain Adjust for ADC B Bank 1 in Single Channel Mode (default from Fuse ROM)

Figure 7-130 GAIN_B1_FGDES Register
76543210
RESERVEDGAIN_B1_FGDUAL
R/W-0x0R/W-0x0
Table 7-140 GAIN_B1_FGDES Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR/W0x0
4:0GAIN_B1_FGDUALR/W0x0

Fine gain adjustment for ADC B bank 1.

7.6.104 PFIR_CFG Register (Address = 0x400) [reset = 0x00]

PFIR_CFG is shown in Figure 7-131 and described in Table 7-141.

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Programmable FIR Mode (default: 0x00)

Figure 7-131 PFIR_CFG Register
76543210
RESERVEDPFIR_SHAREPFIR_MERGEPFIR_SCWPFIR_MODE
R/W-0x0R/W-0x0R/W-0x0R/W-0x0R/W-0x0
Table 7-141 PFIR_CFG Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0x0
6PFIR_SHARER/W0x0

When set, the PFIR on the B channel uses the same coefficients as the PFIR on the A channel. When PFIR_SHARE=0, the B channel filter uses its own set of coefficients (unique from channel A). See Programmable FIR Filter (PFIR) section for usage details.

5PFIR_MERGER/W0x0

When set, the PFIR filters are merged into a single logical filter. This mode processes ADC data samples as if they belong to a single sample stream. Set PFIR_MERGE=1 whenever the ADC is setup in Single Channel Mode.

4:2PFIR_SCWR/W0x0

Side coefficient weight for PFIR. This field determines the weight of the coefficients (except for the center coefficient). Increasing the coefficient weight increases the range of the coefficients at the expense of reduced precision. The LSB weight is 2PFIR_SCW-16, where PFIR_SCW weight can be programmed from 0 to 6. The default is 0 which provides an LSB weight of 2-16.

1:0PFIR_MODER/W0x0

0 : PFIR block is disabled (default)
1 : RESERVED
2 : Enable PFIR block
3 : RESERVED

Note: When using the PFIR, you must also program the filter coefficients.

Note: All PFIR_* register should only be changed when JESD_EN=0.

7.6.105 PFIR_A0 Register (Address = 0x418) [reset = 0x0]

PFIR_A0 is shown in Figure 7-132 and described in Table 7-142.

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PFIR Coefficient A0

Figure 7-132 PFIR_A0 Register
15141312111098
RESERVEDPFIR_A0
R/W-0x0R/W-0x0
76543210
PFIR_A0
R/W-0x0
Table 7-142 PFIR_A0 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_A0R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the first tap for the ADC A programmable FIR filter in Dual Channel Mode or the first tap for the programmable FIR filter in Single Channel Mode.

7.6.106 PFIR_A1 Register (Address = 0x41A) [reset = 0x0]

PFIR_A1 is shown in Figure 7-133 and described in Table 7-143.

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PFIR Coefficient A1

Figure 7-133 PFIR_A1 Register
15141312111098
RESERVEDPFIR_A1
R/W-0x0R/W-0x0
76543210
PFIR_A1
R/W-0x0
Table 7-143 PFIR_A1 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_A1R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the second tap for the ADC A programmable FIR filter in Dual Channel Mode or the second tap for the programmable FIR filter in Single Channel Mode.

7.6.107 PFIR_A2 Register (Address = 0x41C) [reset = 0x0]

PFIR_A2 is shown in Figure 7-134 and described in Table 7-144.

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PFIR Coefficient A2

Figure 7-134 PFIR_A2 Register
15141312111098
RESERVEDPFIR_A2
R/W-0x0R/W-0x0
76543210
PFIR_A2
R/W-0x0
Table 7-144 PFIR_A2 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_A2R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the third tap for the ADC A programmable FIR filter in Dual Channel Mode or the third tap for the programmable FIR filter in Single Channel Mode.

7.6.108 PFIR_A3 Register (Address = 0x41E) [reset = 0x0]

PFIR_A3 is shown in Figure 7-135 and described in Table 7-145.

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PFIR Coefficient A3

Figure 7-135 PFIR_A3 Register
15141312111098
RESERVEDPFIR_A3
R/W-0x0R/W-0x0
76543210
PFIR_A3
R/W-0x0
Table 7-145 PFIR_A3 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_A3R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the fourth tap for the ADC A programmable FIR filter in Dual Channel Mode or the fourth tap for the programmable FIR filter in Single Channel Mode.

7.6.109 PFIR_A4 Register (Address = 0x420) [reset = 0x0]

PFIR_A4 is shown in Figure 7-136 and described in Table 7-146.

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PFIR Coefficient A4

Figure 7-136 PFIR_A4 Register
2322212019181716
RESERVEDPFIR_A4
R/W-0x0R/W-0x0
15141312111098
PFIR_A4
R/W-0x0
76543210
PFIR_A4
R/W-0x0
Table 7-146 PFIR_A4 Register Field Descriptions
BitFieldTypeResetDescription
23:18RESERVEDR/W0x0
17:0PFIR_A4R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the fifth tap for the ADC A programmable FIR filter in Dual Channel Mode or the fifth tap for the programmable FIR filter in Single Channel Mode. This is the center tap of the 9-tap filter and therefore has a resolution of 18-bits.

7.6.110 PFIR_A5 Register (Address = 0x423) [reset = 0x0]

PFIR_A5 is shown in Figure 7-137 and described in Table 7-147.

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PFIR Coefficient A5

Figure 7-137 PFIR_A5 Register
15141312111098
RESERVEDPFIR_A5
R/W-0x0R/W-0x0
76543210
PFIR_A5
R/W-0x0
Table 7-147 PFIR_A5 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_A5R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the sixth tap for the ADC A programmable FIR filter in Dual Channel Mode or the sixth tap for the programmable FIR filter in Single Channel Mode.

7.6.111 PFIR_A6 Register (Address = 0x425) [reset = 0x0]

PFIR_A6 is shown in Figure 7-138 and described in Table 7-148.

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PFIR Coefficient A6

Figure 7-138 PFIR_A6 Register
15141312111098
RESERVEDPFIR_A6
R/W-0x0R/W-0x0
76543210
PFIR_A6
R/W-0x0
Table 7-148 PFIR_A6 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_A6R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the seventh tap for the ADC A programmable FIR filter in Dual Channel Mode or the seventh tap for the programmable FIR filter in Single Channel Mode.

7.6.112 PFIR_A7 Register (Address = 0x427) [reset = 0x0]

PFIR_A7 is shown in Figure 7-139 and described in Table 7-149.

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PFIR Coefficient A7

Figure 7-139 PFIR_A7 Register
15141312111098
RESERVEDPFIR_A7
R/W-0x0R/W-0x0
76543210
PFIR_A7
R/W-0x0
Table 7-149 PFIR_A7 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_A7R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the eighth tap for the ADC A programmable FIR filter in Dual Channel Mode or the eighth tap for the programmable FIR filter in Single Channel Mode.

7.6.113 PFIR_A8 Register (Address = 0x429) [reset = 0x0]

PFIR_A8 is shown in Figure 7-140 and described in Table 7-150.

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PFIR Coefficient A8

Figure 7-140 PFIR_A8 Register
15141312111098
RESERVEDPFIR_A8
R/W-0x0R/W-0x0
76543210
PFIR_A8
R/W-0x0
Table 7-150 PFIR_A8 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_A8R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the ninth tap for the ADC A programmable FIR filter in Dual Channel Mode or the ninth tap for the programmable FIR filter in Single Channel Mode.

7.6.114 PFIR_B0 Register (Address = 0x448) [reset = 0x0]

PFIR_B0 is shown in Figure 7-141 and described in Table 7-151.

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PFIR Coefficient B0

Figure 7-141 PFIR_B0 Register
15141312111098
RESERVEDPFIR_B0
R/W-0x0R/W-0x0
76543210
PFIR_B0
R/W-0x0
Table 7-151 PFIR_B0 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_B0R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the first tap for the ADC B programmable FIR filter in Dual Channel Mode.

7.6.115 PFIR_B1 Register (Address = 0x44A) [reset = 0x0]

PFIR_B1 is shown in Figure 7-142 and described in Table 7-152.

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PFIR Coefficient B1

Figure 7-142 PFIR_B1 Register
15141312111098
RESERVEDPFIR_B1
R/W-0x0R/W-0x0
76543210
PFIR_B1
R/W-0x0
Table 7-152 PFIR_B1 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_B1R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the second tap for the ADC B programmable FIR filter in Dual Channel Mode.

7.6.116 PFIR_B2 Register (Address = 0x44C) [reset = 0x0]

PFIR_B2 is shown in Figure 7-143 and described in Table 7-153.

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PFIR Coefficient B2

Figure 7-143 PFIR_B2 Register
15141312111098
RESERVEDPFIR_B2
R/W-0x0R/W-0x0
76543210
PFIR_B2
R/W-0x0
Table 7-153 PFIR_B2 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_B2R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the third tap for the ADC B programmable FIR filter in Dual Channel Mode.

7.6.117 PFIR_B3 Register (Address = 0x44E) [reset = 0x0]

PFIR_B3 is shown in Figure 7-144 and described in Table 7-154.

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PFIR Coefficient B3

Figure 7-144 PFIR_B3 Register
15141312111098
RESERVEDPFIR_B3
R/W-0x0R/W-0x0
76543210
PFIR_B3
R/W-0x0
Table 7-154 PFIR_B3 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_B3R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the fourth tap for the ADC B programmable FIR filter in Dual Channel Mode.

7.6.118 PFIR_B4 Register (Address = 0x450) [reset = 0x0]

PFIR_B4 is shown in Figure 7-145 and described in Table 7-155.

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PFIR Coefficient B4

Figure 7-145 PFIR_B4 Register
2322212019181716
RESERVEDPFIR_B4
R/W-0x0R/W-0x0
15141312111098
PFIR_B4
R/W-0x0
76543210
PFIR_B4
R/W-0x0
Table 7-155 PFIR_B4 Register Field Descriptions
BitFieldTypeResetDescription
23:18RESERVEDR/W0x0
17:0PFIR_B4R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the fifth tap for the ADC B programmable FIR filter in Dual Channel Mode. This is the center tap of the 9-tap filter and therefore has a resolution of 18-bits.

7.6.119 PFIR_B5 Register (Address = 0x453) [reset = 0x0]

PFIR_B5 is shown in Figure 7-146 and described in Table 7-156.

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PFIR Coefficient B5

Figure 7-146 PFIR_B5 Register
15141312111098
RESERVEDPFIR_B5
R/W-0x0R/W-0x0
76543210
PFIR_B5
R/W-0x0
Table 7-156 PFIR_B5 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_B5R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the sixth tap for the ADC B programmable FIR filter in Dual Channel Mode.

7.6.120 PFIR_B6 Register (Address = 0x455) [reset = 0x0]

PFIR_B6 is shown in Figure 7-147 and described in Table 7-157.

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PFIR Coefficient B6

Figure 7-147 PFIR_B6 Register
15141312111098
RESERVEDPFIR_B6
R/W-0x0R/W-0x0
76543210
PFIR_B6
R/W-0x0
Table 7-157 PFIR_B6 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_B6R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the seventh tap for the ADC B programmable FIR filter in Dual Channel Mode.

7.6.121 PFIR_B7 Register (Address = 0x457) [reset = 0x0]

PFIR_B7 is shown in Figure 7-148 and described in Table 7-158.

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PFIR Coefficient B7

Figure 7-148 PFIR_B7 Register
15141312111098
RESERVEDPFIR_B7
R/W-0x0R/W-0x0
76543210
PFIR_B7
R/W-0x0
Table 7-158 PFIR_B7 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR/W0x0
11:0PFIR_B7R/W0x0

Signed, 2’s complement coefficient for the PFIR filter. This is the eighth tap for the ADC B programmable FIR filter in Dual Channel Mode.

7.6.122 PFIR_B8 Register (Address = 0x459) [reset = 0x0]

PFIR_B8 is shown in Figure 7-149 and described in Table 7-159.

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PFIR Coefficient B8

Figure 7-149 PFIR_B8 Register
15 14 13 12 11 10 9 8
RESERVED PFIR_B8
R/W-0x0 R/W-0x0
7 6 5 4 3 2 1 0
PFIR_B8
R/W-0x0
Table 7-159 PFIR_B8 Register Field Descriptions
Bit Field Type Reset Description
15:12 RESERVED R/W 0x0
11:0 PFIR_B8 R(1)/W 0x0 Signed, 2’s complement coefficient for the PFIR filter. This is the ninth tap for the ADC B programmable FIR filter in Dual Channel Mode.
Read function does not properly return MSB value - the MSB value in readback is always 0.