JAJSEY1C April   2019  – March 2022 ADC12DJ5200RF


  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Comparison
      2. 7.3.2  Analog Inputs
        1. Analog Input Protection
        2. Full-Scale Voltage (VFS) Adjustment
        3. Analog Input Offset Adjust
      3. 7.3.3  ADC Core
        1. ADC Theory of Operation
        2. ADC Core Calibration
        3. Analog Reference Voltage
        4. ADC Overrange Detection
        5. Code Error Rate (CER)
      4. 7.3.4  Temperature Monitoring Diode
      5. 7.3.5  Timestamp
      6. 7.3.6  Clocking
        1. Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. Aperture Delay Ramp Control (TAD_RAMP)
        3. SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. Automatic SYSREF Calibration
      7. 7.3.7  Programmable FIR Filter (PFIR)
        1. Dual Channel Equalization
        2. Single Channel Equalization
        3. Time Varying Filter
      8. 7.3.8  Digital Down Converters (DDC)
        1. Rounding and Saturation
        2. Numerically-Controlled Oscillator and Complex Mixer
          1. NCO Fast Frequency Hopping (FFH)
          2. NCO Selection
          3. Basic NCO Frequency Setting Mode
          4. Rational NCO Frequency Setting Mode
          5. NCO Phase Offset Setting
          6. NCO Phase Synchronization
        3. Decimation Filters
        4. Output Data Format
        5. Decimation Settings
          1. Decimation Factor
          2. DDC Gain Boost
      9. 7.3.9  JESD204C Interface
        1. Transport Layer
        2. Scrambler
        3. Link Layer
        4. 8B/10B Link Layer
          1. Data Encoding (8B/10B)
          2. Multiframes and the Local Multiframe Clock (LMFC)
          3. Code Group Synchronization (CGS)
          4. Initial Lane Alignment Sequence (ILAS)
          5. Frame and Multiframe Monitoring
        5. 64B/66B Link Layer
          1. 64B/66B Encoding
          2. Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. Cyclic Redundancy Check (CRC) Mode
            2. Forward Error Correction (FEC) Mode
          4. Initial Lane Alignment
          5. Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. Physical Layer
          1. SerDes Pre-Emphasis
        7. JESD204C Enable
        8. Multi-Device Synchronization and Deterministic Latency
        9. Operation in Subclass 0 Systems
      10. 7.3.10 Alarm Monitoring
        1. Clock Upset Detection
        2. FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. JESD204C Operating Modes Table
        2. JESD204C Modes continued
        3. JESD204C Transport Layer Data Formats
        4. 64B/66B Sync Header Stream Configuration
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. Serializer Test-Mode Details
        2. PRBS Test Modes
        3. Clock Pattern Mode
        4. Ramp Test Mode
        5. Short and Long Transport Test Mode
          1. Short Transport Test Pattern
        6. D21.5 Test Mode
        7. K28.5 Test Mode
        8. Repeated ILA Test Mode
        9. Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. Foreground Calibration Mode
        2. Background Calibration Mode
        3. Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. SCS
        2. SCLK
        3. SDI
        4. SDO
        5. Streaming Mode
    6. 7.6 SPI Register Map
  8. Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. Design Requirements
          1. Input Signal Path
          2. Clocking
        2. Detailed Design Procedure
          1. Calculating Values of AC-Coupling Capacitors
      2. 8.2.2 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. Design Requirements
          1. Input Signal Path
          2. Clocking
          3. ADC12DJ5200RF
    3. 8.3 Initialization Set Up
  9. Power Supply Recommendations
    1. 9.1 Power Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 143
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
      1.      Mechanical, Packaging, and Orderable Information



Layout Guidelines

There are many critical signals that require specific care during board design:

  1. Analog input signals
  2. CLK and SYSREF
  3. JESD204C data outputs
  4. Power connections
  5. Ground connections

The analog input signals, clock signals and JESD204C data outputs must be routed for excellent signal quality at high frequencies, but should also be routed for maximum isolation from each other. Use the following general practices:

  1. Route using loosely coupled 100-Ω differential traces when possible. This routing minimizes impact of corners and length-matching serpentines on pair impedance.
  2. Provide adequate pair-to-pair spacing to minimize crosstalk, especially with loosely coupled differential traces. Tightly coupled differential traces may be used to reduce self-radiated noise or to improve neighboring trace noise immunity when adequate spacing cannot be provided.
  3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces. Any ground plane pour must have sufficient via connections to the main ground plane of the board. Do not use floating or poorly connected ground pours.
  4. Use smoothly radiused corners. Avoid 45- or 90-degree bends to reduce impedance mismatches.
  5. Incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these locations. Cut-out below the landing pads on one or multiple ground planes to achieve a pad size or stackup height that achieves the needed 50-Ω, single-ended impedance.
  6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include cuts in the ground plane or ground plane clearances associated with power and signal vias and through-hole component leads.
  7. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias at an appropriate spacing as determined by the maximum frequency the trace will transport (<< λMIN/8).
  8. When high-speed signals must transition to another layer using vias, transition as far through the board as possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is not flexible, use back-drilled or buried, blind vias to eliminate stubs. Always place ground vias close to the signal vias when transitioning between layers to provide a nearby ground return path.

Pay particular attention to potential coupling between JESD204C data output routing and the analog input routing. Switching noise from the JESD204C outputs can couple into the analog input traces and show up as wideband noise due to the high input bandwidth fo the ADC. Ideally, route the JESD204C data outputs on a separate layer from the ADC input traces to avoid noise coupling (not shown in the Layout Example section). Tightly coupled traces can also be used to reduce noise coupling.

Impedance mismatch between the CLK± input pins and the clock source can result in reduced amplitude of the clock signal at the ADC CLK± pins due to signal reflections or standing waves. A reduction in the clock amplitude may degrade ADC noise performance, especially at high input frequencies. To avoid this, keep the clock source close to the ADC (as shown in the Layout Example section) or implement impedance matching at the ADC CLK± input pins.

In addition, TI recommends performing signal quality simulations of the critical signal traces before committing to fabrication. Insertion loss, return loss, and time domain reflectometry (TDR) evaluations should be done.

The power and ground connections for the device are also very important. These rules must be followed:

  1. Provide low-resistance connection paths to all power and ground pins.
  2. Use multiple power layers if necessary to access all pins.
  3. Avoid narrow isolated paths that increase connection resistance.
  4. Use a signal, ground, or power circuit board stackup to maximum coupling between the ground and power planes.