JAJSEY1C April 2019 – March 2022 ADC12DJ5200RF
AC-coupling capacitors are used in the input CLK± and JESD204C output data pairs. The capacitor values must be large enough to address the lowest frequency signals of interest, but not so large as to cause excessively long startup biasing times, or unwanted parasitic inductance.
The minimum capacitor value can be calculated based on the lowest frequency signal that is transferred through the capacitor. Given a 50-Ω single-ended clock or data path impedance, good practice is to set the capacitor impedance to be <1 Ω at the lowest frequency of interest. This setting ensures minimal impact on signal level at that frequency. For the CLK± path, the minimum-rated clock frequency is 800 MHz. Therefore, the minimum capacitor value can be calculated from:
Setting Zc = 1 Ω and rearranging gives:
Therefore, a capacitance value of at least 199 pF is needed to provide the low-frequency response for the CLK± path. If the minimum clock frequency is higher than 800 MHz, this calculation can be revisited for that frequency. Similar calculations can be done for the JESD204C output data capacitors based on the minimum frequency in that interface. Capacitors must also be selected for good response at high frequencies, and with dimensions that match the high-frequency signal traces they are connected to. Capacitors of the 0201 size are frequently well suited to these applications.