JAJSN13A October   2021  – October 2024 ADC12DJ800 , ADC12QJ800 , ADC12SJ800

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications
    8. 5.8  Timing Requirements
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Comparison
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Analog Input Protection
        2. 6.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.2.3 Analog Input Offset Adjust
        4. 6.3.2.4 ADC Core
          1. 6.3.2.4.1 ADC Theory of Operation
          2. 6.3.2.4.2 ADC Core Calibration
          3. 6.3.2.4.3 Analog Reference Voltage
          4. 6.3.2.4.4 ADC Over-range Detection
          5. 6.3.2.4.5 Code Error Rate (CER)
      3. 6.3.3 Temperature Monitoring Diode
      4. 6.3.4 Timestamp
      5. 6.3.5 Clocking
        1. 6.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation
        2. 6.3.5.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
        3. 6.3.5.3 Optional CMOS Clock Outputs (ORC, ORD)
        4. 6.3.5.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
          1. 6.3.5.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          2. 6.3.5.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 6.3.6 JESD204C Interface
        1. 6.3.6.1  Transport Layer
        2. 6.3.6.2  Scrambler
        3. 6.3.6.3  Link Layer
        4. 6.3.6.4  8B/10B Link Layer
          1. 6.3.6.4.1 Data Encoding (8B/10B)
          2. 6.3.6.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 6.3.6.4.3 Code Group Synchronization (CGS)
          4. 6.3.6.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 6.3.6.4.5 Frame and Multiframe Monitoring
        5. 6.3.6.5  64B/66B Link Layer
          1. 6.3.6.5.1 64B/66B Encoding
          2. 6.3.6.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
            1. 6.3.6.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
              1. 6.3.6.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
              2. 6.3.6.5.2.1.2 Forward Error Correction (FEC) Mode
          3. 6.3.6.5.3 Initial Lane Alignment
          4. 6.3.6.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 6.3.6.6  Physical Layer
          1. 6.3.6.6.1 SerDes Pre-Emphasis
        7. 6.3.6.7  JESD204C Enable
        8. 6.3.6.8  Multi-Device Synchronization and Deterministic Latency
        9. 6.3.6.9  Operation in Subclass 0 Systems
        10. 6.3.6.10 Alarm Monitoring
          1. 6.3.6.10.1 Clock Upset Detection
          2. 6.3.6.10.2 FIFO Upset Detection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Low Power Mode and High Performance Mode
      2. 6.4.2 JESD204C Modes
        1. 6.4.2.1 JESD204C Transport Layer Data Formats
        2. 6.4.2.2 64B/66B Sync Header Stream Configuration
        3. 6.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 6.4.3 Power-Down Modes
      4. 6.4.4 Test Modes
        1. 6.4.4.1 Serializer Test-Mode Details
        2. 6.4.4.2 PRBS Test Modes
        3. 6.4.4.3 Clock Pattern Mode
        4. 6.4.4.4 Ramp Test Mode
        5. 6.4.4.5 Short and Long Transport Test Mode
          1. 6.4.4.5.1 Short Transport Test Pattern
        6. 6.4.4.6 D21.5 Test Mode
        7. 6.4.4.7 K28.5 Test Mode
        8. 6.4.4.8 Repeated ILA Test Mode
        9. 6.4.4.9 Modified RPAT Test Mode
      5. 6.4.5 Calibration Modes and Trimming
        1. 6.4.5.1 Foreground Calibration Mode
        2. 6.4.5.2 Background Calibration Mode
        3. 6.4.5.3 Low-Power Background Calibration (LPBG) Mode
      6. 6.4.6 Offset Calibration
      7. 6.4.7 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
      2. 6.5.2 SCS
      3. 6.5.3 SCLK
      4. 6.5.4 SDI
      5. 6.5.5 SDO
      6. 6.5.6 Streaming Mode
      7. 6.5.7 SPI_Register_Map Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Analog Front-End Requirements
          2. 7.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 7.2.1.3 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics: DC Specifications

typical values at TA = 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (VFS = 0.8 VPP), fIN = 97 MHz, AIN = –1 dBFS, fCLK = 800MHz, filtered 1 VPP sine-wave clock applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
Resolution Resolution with no missing codes 12 Bits
DNL Differential nonlinearity Maximum positive excursion from ideal step size 0.2 LSB
Maximum negative excursion from ideal step size –0.19
INL Integral nonlinearity Maximum positive excursion from ideal transfer function 1.9 LSB
Maximum negative excursion from ideal transfer function –1.6
ANALOG INPUTS (INA+, INA–, INB+, INB–, INC+, INC–, IND+, IND–)
VOFF Offset error CAL_OS = 0 ±0.4 mV
CAL_OS = 1 ±0.4 mV
VOFF_ADJ Input offset voltage adjustment range Available offset correction range (see OFSx or OFSxCh registers) ±33 mV
VOFF_DRIFT Offset drift Foreground calibration at nominal temperature only, CAL_OS = 1 -1.2 µV/°C
Foreground calibration at each temperature, CAL_OS = 1 0.25
VFS Analog differential input full-scale range Default full-scale voltage (FS_RANGE = 0xA000), measured at DC 750 800 850 mVPPDIFF
Maximum full-scale voltage (FS_RANGE = 0xFFFF), measured at DC 980 1040
Minimum full-scale voltage (FS_RANGE = 0x2000), measured at DC 480 500
VFS_DRIFT Analog differential input full-scale range drift Default FS_RANGE setting, foreground calibration at nominal temperature only, inputs driven by a 50-Ω source, includes effect of RIN drift –0.0015 %/°C
Default FS_RANGE setting, foreground calibration at each temperature, inputs driven by a 50-Ω source, includes effect of RIN drift -.000018
VFS_MATCH Analog differential input full-scale range matching Matching between any two channels (e.g. INA± and INB±), default full-scale voltage, measured at DC 1%
RIN Differential input resistance Center of differential resistance is terminated to VCM, measured at TA = 25°C 92 100 108 Ω
RIN_TEMPCO Input termination linear temperature coefficient 38 mΩ/°C
CIN Single-ended input capacitance Measured at DC 0.6 pF
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)
ΔVBE Temperature diode voltage slope Forced forward current of 100 µA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Offset measurement must be done with the device unpowered or with the PD pin asserted to minimize device self-heating. –1.6 mV/°C
BAND-GAP VOLTAGE OUTPUT (BG)
VBG Internal band-gap reference and VCM reference output voltage IL ≤ 100 µA 1.1 V
VBG_DRIFT VBG output temperature drift IL ≤ 100 µA –117 µV/°C
DIFFERENTIAL CLOCK AND TIMESTAMP INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)
ZT Internal termination Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0 100 Ω
Single-ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0 50
VCM Input common-mode voltage, self-biased Self-biasing common-mode voltage for CLK± when AC-coupled (DEVCLK_LVPECL_EN must be set to 0) 0.3 V
Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1) 0.3
Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0) VA11
CL_DIFF Differential input capacitance Between positive and negative differential input pins 0.1 pF
CL_SE Single-ended input capacitance Each input to ground 0.5 pF
CLOCK AND TRIGGER OUTPUTS (PLLREFO+, PLLREFO–, TRIGOUT+, TRIGOUT–)
VDIFF Differential output voltage, peak-to-peak, DC measurement 100Ω load 400 720 900 mVPP-DIFF
VCM(PLLREFO) PLLREFO± output common-mode voltage 1.31(1) V
VCM(TRIGOUT) TRIGOUT± output common-mode voltage, tracks with VTRIG VTRIG = 1.9 1.31(2) V
VTRIG = 1.1 0.5(2)
ZDIFF Differential output impedance Measured at DC 300 Ω
SERDES OUTPUTS (D[7:0]+, D[7:0]–)
VOD Differential output voltage, peak-to-peak 100-Ω load 600 mVPP-DIFF
VCM Output common-mode voltage AC coupled 0.54 V
ZDIFF Differential output impedance 100 Ω
CMOS INTERFACE (SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, CLKCFG0, CLKCFG1, PLL_EN, PLLREF_SE, ORA, ORB, ORC, ORD, SYNCSE)
VIH High-level input voltage 0.7 V
VIL Low-level input voltage 0.45 V
IIH High-level input current 40 µA
IIL Low-level input current –40 µA
CI Input capacitance 2 pF
VOH High-level output voltage ILOAD = –400 µA 1.65 V
VOL Low-level output voltage ILOAD = 400 µA 150 mV
(1) TI recommends AC-coupling PLLREFO± to the load device when PLLREFO± is enabled.
(2) TI recommends AC-couping TRIGOUT± to the load device when TRIGOUT± is enabled and used as a clock output (from S-PLL). TRIGOUT± can be DC-coupled to the load device when TRIGOUT± is used as a trigger output (from TMSTP±).