The ADC364x includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for clock rates below 40 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer time for the driving amplifier to settle out the signal which can improve the SNR performance of the system.
When powering down the DLL, the acquisition time tracks the clock duty cycle (50% is recommended).
|SAMPLING CLOCK FS (MSPS)||DLL PDN (0x11, D2)||ACQUISITION TIME (tACQ)|
|65||0||TS / 4|
|≤ 40||1||TS / 2|
TS: Sampling clock period