JAJSLQ5C April   2021  – September 2022 ADS127L11

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements (1.65 V ≤ IOVDD ≤ 2 V)
    7. 6.7  Switching Characteristics (1.65 V ≤ IOVDD ≤ 2 V)
    8. 6.8  Timing Requirements (2 V < IOVDD ≤ 5.5 V)
    9. 6.9  Switching Characteristics (2 V < IOVDD ≤ 5.5 V)
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1  Offset Error Measurement
    2. 7.2  Offset Drift Measurement
    3. 7.3  Gain Error Measurement
    4. 7.4  Gain Drift Measurement
    5. 7.5  NMRR Measurement
    6. 7.6  CMRR Measurement
    7. 7.7  PSRR Measurement
    8. 7.8  SNR Measurement
    9. 7.9  INL Error Measurement
    10. 7.10 THD Measurement
    11. 7.11 SFDR Measurement
    12. 7.12 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input (AINP, AINN)
        1. 8.3.1.1 Input Range
      2. 8.3.2 Reference Voltage (REFP, REFN)
        1. 8.3.2.1 Reference Voltage Range
      3. 8.3.3 Clock Operation
        1. 8.3.3.1 Internal Oscillator
        2. 8.3.3.2 External Clock
      4. 8.3.4 Modulator
      5. 8.3.5 Digital Filter
        1. 8.3.5.1 Wideband Filter
        2. 8.3.5.2 Low-Latency Filter (Sinc)
          1. 8.3.5.2.1 Sinc4 Filter
          2. 8.3.5.2.2 Sinc4 + Sinc1 Filter
          3. 8.3.5.2.3 Sinc3 Filter
          4. 8.3.5.2.4 Sinc3 + Sinc1 Filter
      6. 8.3.6 Power Supplies
        1. 8.3.6.1 AVDD1 and AVSS
        2. 8.3.6.2 AVDD2
        3. 8.3.6.3 IOVDD
        4. 8.3.6.4 Power-On Reset (POR)
        5. 8.3.6.5 CAPA and CAPD
      7. 8.3.7 VCM Output Voltage
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Scalable Speed Modes
      2. 8.4.2 Idle Mode
      3. 8.4.3 Standby Mode
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Reset
        1. 8.4.5.1 RESET Pin
        2. 8.4.5.2 Reset by SPI Register Write
        3. 8.4.5.3 Reset by SPI Input Pattern
      6. 8.4.6 Synchronization
        1. 8.4.6.1 Synchronized Control Mode
        2. 8.4.6.2 Start/Stop Control Mode
        3. 8.4.6.3 One-Shot Control Mode
      7. 8.4.7 Conversion-Start Delay Time
      8. 8.4.8 Calibration
        1. 8.4.8.1 OFFSET2, OFFSET1, OFFSET0 Calibration Registers (Addresses 9h, Ah, Bh)
        2. 8.4.8.2 GAIN2, GAIN1, GAIN0 Calibration Registers (Addresses 0Ch, 0Dh, 0Eh)
        3. 8.4.8.3 Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface (SPI)
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Serial Data Input (SDI)
        4. 8.5.1.4 Serial Data Output/Data Ready (SDO/DRDY)
      2. 8.5.2 SPI Frame
      3. 8.5.3 SPI CRC
      4. 8.5.4 Register Map CRC
      5. 8.5.5 Full-Duplex Operation
      6. 8.5.6 Device Commands
        1. 8.5.6.1 No-Operation
        2. 8.5.6.2 Read Register Command
        3. 8.5.6.3 Write Register Command
      7. 8.5.7 Read Conversion Data
        1. 8.5.7.1 Conversion Data
        2. 8.5.7.2 Data Ready
          1. 8.5.7.2.1 DRDY
          2. 8.5.7.2.2 SDO/DRDY
          3. 8.5.7.2.3 DRDY Bit
          4. 8.5.7.2.4 Clock Counting
        3. 8.5.7.3 STATUS Header
      8. 8.5.8 Daisy-Chain Operation
      9. 8.5.9 3-Wire SPI Mode
        1. 8.5.9.1 3-Wire SPI Mode Frame Reset
    6. 8.6 Registers
      1. 8.6.1  DEV_ID Register (Address = 0h) [reset = 00h]
      2. 8.6.2  REV_ID Register (Address = 1h) [reset = xxh]
      3. 8.6.3  STATUS Register (Address = 2h) [reset = x1100xxxb]
      4. 8.6.4  CONTROL Register (Address = 3h) [reset = 00h]
      5. 8.6.5  MUX Register (Address = 4h) [reset = 00h]
      6. 8.6.6  CONFIG1 Register (Address = 5h) [reset = 00h]
      7. 8.6.7  CONFIG2 Register (Address = 6h) [reset = 00h]
      8. 8.6.8  CONFIG3 Register (Address = 7h) [reset = 00h]
      9. 8.6.9  CONFIG4 Register (Address = 8h) [reset = 00h]
      10. 8.6.10 OFFSET2, OFFSET1, OFFSET0 Registers (Addresses = 9h, Ah, Bh) [reset = 00h, 00h, 00h]
      11. 8.6.11 GAIN2, GAIN1, GAIN0 Registers (Addresses = Ch, Dh, Eh) [reset = 40h, 00h, 00h]
      12. 8.6.12 CRC Register (Address = Fh) [reset = 00h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 SPI Operation
      2. 9.1.2 Input Driver
      3. 9.1.3 Antialias Filter
      4. 9.1.4 Reference Voltage
      5. 9.1.5 Simultaneous-Sampling Systems
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD1 =  5 V, AVDD2 = 1.8 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VIN = 0 V, VCM = 2.5 V, VREFP =  4.096 V, VREFN = 0 V, high-reference range, 1x input range, fCLK = 25.6 MHz (high-speed mode), fCLK = 3.2 MHz (low-speed mode), input precharge buffers on, and reference precharge buffer on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS, HIGH-SPEED MODE
Input current,
differential input voltage		 Precharge buffers off 95 µA/V
Precharge buffers off, 2x input range 47
Precharge buffers on ±3 µA
Input current drift,
differential input voltage
 Precharge buffers off 3 nA/V/°C
Precharge buffers off, 2x input range 1.5
Precharge buffers on 5 nA/°C
Input current,
common-mode input voltage		 Precharge buffers off 5 µA/V
Precharge buffers off, 2x input range 2.5
Precharge buffers on ±3 µA
ANALOG INPUTS, LOW-SPEED MODE
Input current,
differential input voltage		 Precharge buffers off 12 µA/V
Precharge buffers off, 2x input range 6
Precharge buffers on ±0.4 µA
Input current drift,
differential input voltage		 Precharge buffers off 1 nA/V/°C
Precharge buffers off, 2x input range 0.5
Precharge buffers on 0.2 nA/°C
Input current,
common-mode input voltage		 Precharge buffers off 0.6 µA/V
Precharge buffers off, 2x input range 0.3
Precharge buffers on ±0.4 µA
DC PERFORMANCE
Resolution
OSR ≥ 64

 24 Bits
Noise See Noise Performance for details
fDATA Output data rate High-speed mode, low-latency filter 0.08 1067 kSPS
High-speed mode, wideband filter 3.125 400
Low-speed mode, low-latency filter 0.01 133
Low-speed mode, wideband filter 0.390625 50
INL
 Integral nonlinearity Best-fit method 0.9 5.5 ppm of FSR
TA = 25°C to 85°C 4
Offset error TA = 25°C –250 ±30 250 µV
Offset drift 50 200 nV/°C
Gain error TA = 25°C –2000 ±200 2000 ppm of FSR
Gain drift 0.6 1.9 ppm of FSR/°C
NMRR Normal-mode rejection ratio fIN = 50 Hz (±1 Hz), fDATA = 50 SPS 100 dB
fIN = 60 Hz (±1 Hz), fDATA = 60 SPS 100
CMRR Common-mode rejection ratio At dc 110 130 dB
Up to 10 kHz 115
At dc, 2x input range 95
PSRR Power-supply rejection ratio AVDD1, dc 100 120 dB
AVDD2, dc 115 130
IOVDD, dc 115 130
AC PERFORMANCE, HIGH-SPEED MODE
DR Dynamic range Inputs shorted,
OSR = 64,
fDATA = 200 kSPS		 Wideband filter 109 111.5 dB
Wideband filter,
VREF = 2.5 V		 107.5
Wideband filter,
VREF = 2.5 V,
2x input range		 108.5
Low-latency filter 112 114
Low-latency filter,
VREF = 2.5 V		 110.5
Low-latency filter,
VREF = 2.5 V,
2x input range		 111
SNR Signal-to-noise ratio fIN = 1 kHz,
VIN = –0.2 dBFS,
OSR = 64,
fDATA = 200 kSPS,
9 harmonics		 Wideband filter 110 dB
Wideband filter,
VREF = 2.5 V		 106
Wideband filter,
VREF = 2.5 V,
2x input range		 107
Low-latency filter 112
Low-latency filter,
VREF = 2.5 V		 108.5
Low-latency filter,
VREF = 2.5 V,
2x input range		 110
THD Total harmonic distortion
fIN = 1 kHz,
VIN = –0.2 dBFS,
OSR = 64, 
fDATA = 200 kSPS,
9 harmonics		 Wideband filter –120 dB
SFDR Spurious-free dynamic range fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64 120 dB
AC PERFORMANCE, LOW-SPEED MODE
DR Dynamic range Inputs shorted,
OSR = 64,
fDATA = 25 kSPS		 Wideband filter 109 112 dB
Wideband filter,
VREF = 2.5 V		 107.5
Wideband filter,
VREF = 2.5 V,
2x input range		 108.5
Low-latency filter 111.5 114.5
Low-latency filter,
VREF = 2.5 V		 110.5
Low-latency filter,
VREF = 2.5 V,
2x input range		 111.5
SNR Signal-to-noise ratio fIN = 1 kHz,
VIN = –0.2 dBFS,
OSR = 64,
fDATA = 25 kSPS		 Wideband filter 110 dB
Wideband filter,
VREF = 2.5 V		 106
Wideband filter,
VREF = 2.5 V,
2x input range		 108
Low-latency filter 112
Low-latency filter,
VREF = 2.5 V		 108
Low-latency filter,
VREF = 2.5 V,
2x input range		 110
THD Total harmonic distortion fIN = 1 kHz,
VIN = –0.2 dBFS,
OSR = 64,
fDATA = 25 kSPS,
9 harmonics		 Wideband filter –125 dB
SFDR Spurious-free dynamic range fIN = 1 kHz, VIN = –0.2 dBFS, OSR = 64 120 dB
WIDEBAND FILTER CHARACTERISTICS
Pass-band frequency Within envelope of pass-band ripple 0.4 ∙ fDATA Hz
–0.1-dB frequency 0.4125 ∙ fDATA
–3-dB frequency 0.4374 ∙ fDATA
Pass-band ripple –0.0004 0.0004 dB
Stop-band frequency At stop-band attenuation 0.5 · fDATA Hz
Stop-band attenuation(1) 106 dB
Group delay 34 / fDATA s
Settling time 68 / fDATA s
VOLTAGE REFERENCE INPUTS
REFP and REFN input current,
differential reference voltage		 REFP precharge buffer off, high-speed mode 190 µA/V
REFP precharge buffer off, low-speed mode 80
REFP input current,
differential reference voltage		 REFP precharge buffer on ±2 µA
REFP and REFN
input current drift		 REFP precharge buffer off, high-speed mode 10 nA/℃
REFP precharge buffer off, low-speed mode 10
REFP input current drift
 REFP precharge buffer on 10
INTERNAL OSCILLATOR
Frequency High-speed mode 25.4 25.6 25.8 MHz
Low-speed mode 3.17 3.2 3.23
VCM OUTPUT VOLTAGE
Output voltage (AVDD1 + AVSS) / 2 V
Accuracy –1% ±0.1% 1%
Voltage noise 1-kHz bandwidth 25 µVRMS
Start-up time CL = 100 nF 1 ms
Capacitive load 100 nF
Resistive load 2 kΩ
Short-circuit current limit 10 mA
DIGITAL INPUTS/OUTPUTS
VOL Logic-low output level OUT_DRV = 0b, IOL = 2 mA 0.2 ∙ IOVDD V
OUT_DRV = 1b, IOL = 1 mA 0.2 ∙ IOVDD
VOH Logic-high output level OUT_DRV = 0b, IOH = –2 mA 0.8 ∙ IOVDD V
OUT_DRV = 1b, IOH = –1 mA 0.8 ∙ IOVDD
Input hysteresis 150 mV
Input current Excluding RESET pin –1 1 µA
RESET pin pullup resistor 20 kΩ
ANALOG SUPPLY CURRENT
IAVDD1, IAVSS AVDD1 and AVSS current
(All buffers off)		 High-speed mode 1.7 1.85 mA
Low-speed mode 0.25 0.3
Standby mode 35 µA
Power-down mode 5
AVDD1 and AVSS additional
current (per buffer function)		 AINx precharge buffer, high-speed mode 1.35 1.9 mA
AINx precharge buffer, low-speed mode 0.2 0.3
REFP precharge buffer, high-speed mode 1.5 1.6
REFP precharge buffer, low-speed mode 0.4 0.45
VCM buffer 0.1
IAVDD2, IAVSS AVDD2 and AVSS current High-speed mode 3.5 3.8 mA
Low-speed mode 0.85 0.95
Standby mode 60 µA
Power-down mode 1
DIGITAL SUPPLY CURRENT
IIOVDD IOVDD current High-speed mode, wideband filter, OSR = 32 2.1 2.7 mA
High-speed mode, low-latency filter, OSR = 32 0.6 1
Low-speed mode, wideband filter, OSR = 32 0.3 0.4
Low-speed mode, low-latency filter, OSR = 32 0.1 0.2
Standby mode, external clock 10 µA
Standby mode, internal oscillator 40
Power-down mode 10
POWER DISSIPATION
PD Power dissipation AVDD2 = 1.8 V, precharge buffers off High-speed mode, wideband filter 18.6 mW
High-speed mode,
low-latency filter		 15.9
Low-speed mode, wideband filter 3.3
Low-speed mode,
low-latency filter		 3.0
(1) Stop-band attenuation as provided by the digital filter. Input frequencies in the stop band intermodulate with the chop frequency beginning at fMOD / 32, which results in stop-band attenuation exceeding 106 dB. See the wideband filter stop-band attenuation figure for details.